Routability-driven placement for hierarchical mixed-size circuit designs. - Meng-Kai Hsu; Yi-Fang Chen; Chau-Chin Huang; Tung-Chieh Chen; Yao-Wen Chang (DAC, 2013)

Routability-Driven Blockage-Aware Macro Placement. - Yi-Fang Chen; Chau-Chin Huang; Chien-Hsiung Chiou; Yao-Wen Chang; Chang-Jen Wang (DAC, 2014)

NTUplace4h: A Novel Routability-Driven Placement Algorithm for Hierarchical Mixed-Size Circuit Designs. - Meng-Kai Hsu; Yi-Fang Chen; Chau-Chin Huang; Sheng Chou; Tzu-Hen Lin; Tung-Chieh Chen; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Detailed-Routing-Driven analytical standard-cell placement. - Chau-Chin Huang; Chien-Hsiung Chiou; Kai-Han Tseng; Yao-Wen Chang (ASP-DAC, 2015)

Detailed-Routability-Driven Analytical Placement for Mixed-Size Designs with Technology and Region Constraints. - Chau-Chin Huang; Hsin-Ying Lee; Bo-Qiao Lin; Sheng-Wei Yang; Chin-Hao Chang; Szu-To Chen; Yao-Wen Chang (ICCAD, 2015)

Timing-driven cell placement optimization for early slack histogram compression. - Chau-Chin Huang; Yen-Chun Liu; Yu-Sheng Lu; Yun-Chih Kuo; Yao-Wen Chang; Sy-Yen Kuo (DAC, 2016)

Graph-Based Logic Bit Slicing for Datapath-Aware Placement. - Chau-Chin Huang; Bo-Qiao Lin; Hsin-Ying Lee; Yao-Wen Chang; Kuo-Sheng Wu; Jun-Zhi Yang (DAC, 2017)

Clock-aware placement for large-scale heterogeneous FPGAs. - Yun-Chih Kuo; Chau-Chin Huang; Shih-Chun Chen; Chun-Han Chiang; Yao-Wen Chang; Sy-Yen Kuo (ICCAD, 2017)

End-to-End Industrial Study of Retiming. - Cunxi Yu; Chau-Chin Huang; Gi-Joon Nam; Mihir Choudhury; Victor N. Kravets; Andrew Sullivan; Maciej J. Ciesielski; Giovanni De Micheli (ISVLSI, 2018)

NTUplace4dr: A Detailed-Routing-Driven Placer for Mixed-Size Circuit Designs With Technology and Region Constraints. - Chau-Chin Huang; Hsin-Ying Lee; Bo-Qiao Lin; Sheng-Wei Yang; Chin-Hao Chang; Szu-To Chen; Yao-Wen Chang; Tung-Chieh Chen; Ismail Bustany (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Latch Clustering for Timing-Power Co-Optimization. - Chau-Chin Huang; Gustavo E. Téllez; Gi-Joon Nam; Yao-Wen Chang (DAC, 2020)

Clock-Aware Placement for Large-Scale Heterogeneous FPGAs. - Jianli Chen; Zhifeng Lin; Yun-Chih Kuo; Chau-Chin Huang; Yao-Wen Chang; Shih-Chun Chen; Chun-Han Chiang; Sy-Yen Kuo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)