Combining technology mapping and placement for delay-optimization in FPGA designs. - Chau-Shen Chen; Yu-Wen Tsay; TingTing Hwang; Allen C.-H. Wu; Youn-Long Lin (ICCAD, 1993)

Combining technology mapping and placement for delay-minimization in FPGA designs. - Chau-Shen Chen; Yu-Wen Tsay; TingTing Hwang; Allen C.-H. Wu; Youn-Long Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Layout Driven Selecting and Chaining of Partial Scan. - Chau-Shen Chen; Kuang-Hui Lin; TingTing Hwang (DAC, 1996)

Low Power FPGA Design - A Re-engineering Approach. - Chau-Shen Chen; TingTing Hwang; C. L. Liu 001 (DAC, 1997)

Layout Driven Selection and Chaining of Partial Scan Flip-Flops. - Chau-Shen Chen; TingTing Hwang (J. Electron. Test., 1998)

Architecture driven circuit partitioning. - Chau-Shen Chen; TingTing Hwang; C. L. Liu 001 (IEEE Trans. Very Large Scale Integr. Syst., 2001)