Multiple path sensitization for hierarchical circuit testing. - Chau-Chin Su; Charles R. Kime (ITC, 1990)

Computer-aided design of pseudoexhaustive BIST for semiregular circuits. - Chau-Chin Su; Charles R. Kime (ITC, 1990)

A Universal BIST Methodology for Interconnects. - Chiyuan Chang; Chauchin Su (ISCAS, 1993)

ECCSyn: a Synthesis Tool for ECC Circuits. - Chauchin Su; Jyrghong Wang (ISCAS, 1993)

A Serial-Scan Test-Vector-Compression Methodology. - Chauchin Su; Kychin Hwang (ITC, 1993)

Random Testing of Interconnects in A Boundary Scan Environment. - Chauchin Su (EDAC-ETC-EUROASIC, 1994)

Hierarchical Techniques for Symbolic Analysis of Large Electronic Circuits. - Shyh-Jye Jou; Mei-Fang Perng; Chauchin Su; C. K. Wang (ISCAS, 1994)

An IDDQ Based Built-in Concurrent Test Technique for Interconnects in a Boundary-Scan Environment. - Chauchin Su; Kychin Hwang; Shyh-Jye Jou (ITC, 1994)

Impulse response fault model and fault extraction for functional level analog circuit diagnosis. - Chauchin Su; Shenshung Chiang; Shyh-Jye Jou (ICCAD, 1995)

A Parallel Event-Driven MOS Timing Simulator on Distributed-Memory Multiprocessors. - Wen-Hsing Hsieh; Shyh-Jye Jou; Chauchin Su (ISCAS, 1995)

Circuits Design Optimization Using Symbolic Approach. - Shyh-Jye Jou; Kou-Fong Liu; Chauchin Su (ISCAS, 1995)

Syndrome Simulation And Syndrome Test For Unscanned Interconnects. - Chauchin Su; Shyh-Shen Hwang; Shyh-Jye Jou; Yuan-Tzu Ting (Asian Test Symposium, 1996)

Decentralized BIST for 1149.1 and 1149.5 Based Interconnects. - Chauchin Su; Shyh-Jye Jou; Yuan-Tzu Ting (ED&TC, 1996)

Metrology for analog module testing using analog testability bus. - Chauchin Su; Yue-Tsang Chen; Shyh-Jye Jou; Yuan-Tzu Ting (ICCAD, 1996)

Structural approach for performance driven ECC circuit synthesis. - Chauchin Su; Kathy Y. Chen; Shyh-Jye Jou (ASP-DAC, 1997)

Analog signal metrology for mixed signal ICs. - Chauchin Su; Yi-Ren Cheng; Yue-Tsang Chen; Shing Tenchen (Asian Test Symposium, 1997)

Parasitic Effect Removal for Analog Measurement in P1149.4 Environment. - Chauchin Su; Yue-Tsang Chen; Shyh-Jye Jou (ITC, 1997)

A pipelined multiplier-accumulator using a high-speed, low-power static and dynamic full adder design. - Shyh-Jye Jou; Chang-Yu Chen; En-Chung Yang; Chau-Chin Su (IEEE J. Solid State Circuits, 1997)

Analog Module Metrology Using MNABST-1 P1149.4 Test Chip. - Yue-Tsang Chen; Chauchin Su (Asian Test Symposium, 1998)

Comprehensive Interconnect BIST Methodology for Virtual Socket Interface. - Chauchin Su; Yue-Tsung Chen (Asian Test Symposium, 1998)

A linear optimal test generation algorithm for interconnect testing. - Chauchin Su (ICCAD, 1998)

Boundary scan BIST methodology for reconfigurable systems. - Chauchin Su; Shung-Won Jeng; Yue-Tsang Chen (ITC, 1998)

Analog Metrology and Stimulus Selection in a Noisy Environment. - Chauchin Su; Yue-Tsang Chen; Chung-Len Lee 001 (Asian Test Symposium, 1999)

Decentralized BIST Methodology for System Level Interconnects. - Chauchin Su; Shyh-Jye Jou (J. Electron. Test., 1999)

A methodology for fault model development for hierarchical linear systems. - Yin-Chao Huang; Chung-Len Lee 001; Jun-Weir Lin; Jwu E. Chen; Chauchin Su (Asian Test Symposium, 2000)

Is IDDQ testing not applicable for deep submicron VLSI in year 2011? - Chih-Wen Lu; Chauchin Su; Chung-Len Lee 001; Jwu E. Chen (Asian Test Symposium, 2000)

All Digital Built-in Delay and Crosstalk Measurement for On-Chip Buses. - Chauchin Su; Yue-Tsang Chen; Mu-Jeng Huang; Gen-Nan Chen; Chung-Len Lee 001 (DATE, 2000)

Crosstalk Effect Removal for Analog Measurement in Analog Test Bus. - Chauchin Su; Yue-Tsang Chen (VTS, 2000)

A Behavior-Level Fault Model for the Closed-Loop Operational Amplifier. - Yeong-Jar Chang; Chung-Len Lee 001; Jwu E. Chen; Chauchin Su (J. Inf. Sci. Eng., 2000)

Impulse Response Fault Model and Fault Extraction for Functional Level Analog Circuit Diagnosis. - Chauchin Su; Yue-Tsang Chen; Shenshung Chiang (J. Inf. Sci. Eng., 2000)

Intrinsic response extraction for the removal of the parasiticeffects in analog test buses. - Chauchin Su; Yue-Tsang Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

A computer aided engineering system for memory BIST. - Chauchin Su; Shih-Ching Hsiao; Hau-Zen Zhau; Chung-Len Lee 001 (ASP-DAC, 2001)

Configuration free SoC interconnect BIST methodology. - Chauchin Su; Wenliang Tseng (ITC, 2001)

Test Waveform Shaping in Mixed Signal Test Bus by Pre-Equalization. - Yue-Tsang Chen; Chauchin Su (VTS, 2001)

Fault Diagnosis for Linear Analog Circuits. - Jun-Weir Lin; Chung-Len Lee 001; Chauchin Su; Jwu E. Chen (J. Electron. Test., 2001)

Intrinsic response for analog module testing using an analog testability bus. - Chauchin Su; Yue-Tsang Chen; Shyh-Jye Jou (ACM Trans. Design Autom. Electr. Syst., 2001)

A Self Calibrated ADC BIST Methodology. - Hung-Kai Chen 001; Chih-Hu Wang; Chau-Chin Su (VTS, 2002)

Guest Editorial. - Kuen-Jong Lee; Chau-Chin Su (J. Electron. Test., 2002)

Analysis of Application of the IDDQ Technique to the Deep Sub-Micron VLSI Testing. - Chih-Wen Lu; Chung-Len Lee 001; Chauchin Su; Jwu-E Chen (J. Electron. Test., 2002)

A novel LCD driver testing technique using logic test channels. - Chauchin Su; Wei-Juo Wang; Chih-Hu Wang; I. S. Tseng (ASP-DAC, 2003)

1149.4 Based On-Line Quiescent State Monitoring Technique. - Chauchin Su; Chih-Hu Wang; Wei-Juo Wang; I. S. Tseng (VTS, 2003)

A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-Micron VLSI. - Katherine Shu-Min Li; Chung-Len Lee 001; Chauchin Su; Jwu E. Chen (Asian Test Symposium, 2004)

Oscillation ring based interconnect test scheme for SOC. - Katherine Shu-Min Li; Chung-Len Lee 001; Chauchin Su; Jwu E. Chen (ASP-DAC, 2005)

Finite State Machine Synthesis for At-Speed Oscillation Testability. - Katherine Shu-Min Li; Chung-Len Lee 001; Tagin Jiang; Chauchin Su; Jwu E. Chen (Asian Test Symposium, 2005)

A spread spectrum clock generator for SATA-II. - Wei-Ta Chen; Jen-Chien Hsu; Hong-Wen Lune; Chauchin Su (ISCAS (3), 2005)

A Digital BIST Methodology for Spread Spectrum Clock Generators. - Maohsuan Chou; Jen-Chien Hsu; Chauchin Su (ATS, 2006)

Estimation of Loss Coefficients of Nonlinear Rubber Using Iterative H∞ Filter. - Chih-Hu Wang; Bore-Kuen Lee; Wei-Hang Tseng; Chung-Hsi Fu; Chauchin Su; Chien-Nan Jimmy Liu (SMC, 2006)

Passive Reduced-Order Macro-Modeling for Linear Time-Delay Interconnect Systems. - Wenliang Tseng; Chien-Nan Jimmy Liu; Chauchin Su (IEICE Trans. Electron., 2006)

IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults. - Katherine Shu-Min Li; Chauchin Su; Yao-Wen Chang; Chung-Len Lee 001; Jwu E. Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

A Test and Diagnosis Methodology for RF Transceivers. - Hung-Kai Chen 001; Chauchin Su (ATS, 2007)

IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection. - Katherine Shu-Min Li; Chung-Len Lee 001; Chauchin Su; Jwu E. Chen (J. Electron. Test., 2007)

Multilevel Full-Chip Routing With Testability and Yield Enhancement. - Katherine Shu-Min Li; Yao-Wen Chang; Chung-Len Lee 001; Chauchin Su; Jwu E. Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

A Scalable Digitalized Buffer for Gigabit I/O. - Hungwen Lu; Chauchin Su; Chien-Nan Jimmy Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

Long-Range Prediction for Real-Time MPEG Video Traffic: An Hinfty Filter Approach. - Chih-Hu Wang; Bor-Sen Chen; Bore-Kuen Lee; Tsu-Tian Lee; Chien-Nan Jimmy Liu; Chauchin Su (IEEE Trans. Circuits Syst. Video Technol., 2008)

BIST for Measuring Clock Jitter of Charge-Pump Phase-Locked Loops. - Jen-Chien Hsu; Chauchin Su (IEEE Trans. Instrum. Meas., 2008)

Analysis and Design of Wide-Band Digital Transmission in an Electrostatic-Coupling Intra-Body Communication System. - Yuhwai Tseng; Chauchin Su; Chien-Nan Jimmy Liu (IEICE Trans. Commun., 2009)

A Tree-Topology Multiplexer for Multiphase Clock System. - Hungwen Lu; Chauchin Su; Chien-Nan Jimmy Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Design of an All-Digital LVDS Driver. - Hungwen Lu; Hsin-Wen Wang; Chauchin Su; Chien-Nan Jimmy Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus. - Katherine Shu-Min Li; Chung-Len Lee 001; Chauchin Su; Jwu E. Chen (IEEE Trans. Very Large Scale Integr. Syst., 2009)

A 5Gb/s pulse signaling interface for low power on-chip data communication. - Hung-Wen Lin; Yingchieh Ho; YingLin Fa; Chauchin Su (ISCAS, 2010)

Measuring the Transmission Characteristic of the Human Body in an Electrostatic-Coupling Intra Body Communication System Using a Square Test Stimulus. - Yuhwai Tseng; Chauchin Su; Chien-Nan Jimmy Liu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Measurement and Evaluation of the Bioelectrical Impedance of the Human Body by Deconvolution of a Square Wave. - Yuhwai Tseng; Chauchin Su; Chien-Nan Jimmy Liu (IEICE Trans. Inf. Syst., 2010)

Timing Jitter and Modulation Profile Extraction for Spread-Spectrum Clocks. - Jen-Chien Hsu; Chauchin Su (IEEE Trans. Instrum. Meas., 2010)

A 0.2-0.6 V ring oscillator design using bootstrap technique. - Yingchieh Ho; Yu-Sheng Yang; Chauchin Su (A-SSCC, 2011)

A sub-100µW multi-functional cardiac signal processor for mobile healthcare applications. - Shu-Yu Hsu; Yingchieh Ho; Yuhwai Tseng; Ting-You Lin; Po-Yao Chang; Jen-Wei Lee; Ju-Hung Hsiao; Siou-Ming Chuang; Tze-Zheng Yang; Po-Chun Liu; Ten-Fang Yang; Ray-Jade Chen; et al. (VLSIC, 2012)

Energy-Effective Sub-Threshold Interconnect Design Using High-Boosting Predrivers. - Yingchieh Ho; Hung-Kai Chen 001; Chauchin Su (IEEE J. Emerg. Sel. Topics Circuits Syst., 2012)

Cumulative Differential Nonlinearity Testing of ADCs. - Hung-Kai Chen 001; Yingchieh Ho; Chauchin Su (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

A 0.1-0.3 V 40-123 fJ/bit/ch On-Chip Data Link With ISI-Suppressed Bootstrapped Repeaters. - Yingchieh Ho; Chauchin Su (IEEE J. Solid State Circuits, 2012)

A 0.09 µW Low Power Front-End Biopotential Amplifier for Biosignal Recording. - Yuhwai Tseng; Yingchieh Ho; Shuoting Kao; Chauchin Su (IEEE Trans. Biomed. Circuits Syst., 2012)

Design of a Subthreshold-Supply Bootstrapped CMOS Inverter Based on an Active Leakage-Current Reduction Technique. - Yingchieh Ho; Chiachi Chang; Chauchin Su (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A Near-Threshold 480 MHz 78 µW All-Digital PLL With a Bootstrapped DCO. - Yingchieh Ho; Yu-Sheng Yang; Chiachi Chang; Chauchin Su (IEEE J. Solid State Circuits, 2013)

A low-power analog-to-digital converter with digitalized amplifier for PAM systems. - Yingchieh Ho; Chou-Ming Kuo; Chauchin Su (MWSCAS, 2014)

A 48.6-to-105.2 µW Machine Learning Assisted Cardiac Sensor SoC for Mobile Healthcare Applications. - Shu-Yu Hsu; Yingchieh Ho; Po-Yao Chang; Chauchin Su; Chen-Yi Lee (IEEE J. Solid State Circuits, 2014)

A 0.5V/22 μW low power transceiver IC for use in ESC intra-body communication system. - Yuhwai Tseng; Ting-You Lin; Songwen Yau; Yingchieh Ho; Chauchin Su (ISOCC, 2016)

LDMOS Channel Thermometer Based on a Thermal Resistance Sensor for Balancing Temperature in Monolithic Power ICs. - Ting-You Lin; Yingchieh Ho; Chauchin Su (Sensors, 2017)

Package and Chip Accelerated Aging Methods for Power MOSFET Reliability Evaluation. - Ting-You Lin; Chauchin Su; Chung-Chih Hung; Karuna Nidhi; Chily Tu; Shao-Chang Huang (DATE, 2019)