A 10Gbps Burst-Mode CDR Circuit in 0.18μm CMOS. - Che-Fu Liang; Sy-Chyuan Hwu; Shen-Iuan Liu (CICC, 2006)

A 14-band Frequency Synthesizer for MB-OFDM UWB Application. - Che-Fu Liang; Shen-Iuan Liu; Yen-Horng Chen; Tzu-Yi Yang; Gin-Kou Ma (ISSCC, 2006)

A Calibrated Pulse Generator for Impulse-Radio UWB Applications. - Che-Fu Liang; Shih-Tsai Liu; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2006)

A Multi-Band Burst-Mode Clock and Data Recovery Circuit. - Che-Fu Liang; Sy-Chyuan Hwu; Shen-Iuan Liu (IEICE Trans. Electron., 2007)

Spur-Suppression Techniques for Frequency Synthesizers. - Che-Fu Liang; Hsin-Hua Chen; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

A 20/10/5/2.5Gb/s Power-scaling Burst-Mode CDR Circuit Using GVCO/Div2/DFF Tri-mode Cells. - Che-Fu Liang; Shen-Iuan Liu (ISSCC, 2008)

A Digital Calibration Technique for Charge Pumps in Phase-Locked Systems. - Che-Fu Liang; Shin-Hua Chen; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2008)

A Jitter-Tolerance-Enhanced CDR Using a GDCO-Based Phase Detector. - Che-Fu Liang; Sy-Chyuan Hwu; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2008)

10-Gb/s Inductorless CDRs With Digital Frequency Calibration. - Che-Fu Liang; Hong-Lin Chu; Shen-Iuan Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

A Single-PLL UWB Frequency Synthesizer Using Multiphase Coupled Ring Oscillator and Current-Reused Multiplier. - Jung-Yu Chang; Che-Wei Fan; Che-Fu Liang; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

An injection-locked ring PLL with self-aligned injection window. - Che-Fu Liang; Keng-Jan Hsiao (ISSCC, 2011)

A wideband fractional-N ring PLL with fractional-spur suppression using spectrally shaped segmentation. - Tsung-Kai Kao; Che-Fu Liang; Hsien-Hsiang Chiu; Michael Ashburn (ISSCC, 2013)

15.3 A 2.4GHz ADPLL with digital-regulated supply-noise-insensitive and temperature-self-compensated ring DCO. - Yi-Chieh Huang; Che-Fu Liang; Hsien-Sheng Huang; Ping-Ying Wang (ISSCC, 2014)

A 1V fractional-N PLL with nonlinearity-insensitive modulator. - Yi-Chieh Huang; Che-Fu Liang; Ping-Ying Wang (A-SSCC, 2015)

10.8 A wideband fractional-N ring PLL using a near-ground pre-distorted switched-capacitor loop filter. - Che-Fu Liang; Ping-Ying Wang (ISSCC, 2015)