An efficient approach for error diagnosis in HDL design. - Che-Hua Shih; Jing-Yang Jou (ISCAS (4), 2003)

On compliance test of on-chip bus for SOC. - Hue-Min Lin; Chia-Chih Yen; Che-Hua Shih; Jing-Yang Jou (ASP-DAC, 2004)

Stimulus generation for interface protocol verification using the nondeterministic extended finite state machine model. - Che-Hua Shih; Juinn-Dar Huang; Jing-Yang Jou (HLDVT, 2005)

FSM-based transaction-level functional coverage for interface compliance verification. - Man-Yun Su; Che-Hua Shih; Juinn-Dar Huang; Jing-Yang Jou (ASP-DAC, 2006)

Automatic Verification Stimulus Generation for Interface Protocols Modeled With Non-Deterministic Extended FSM. - Che-Hua Shih; Juinn-Dar Huang; Jing-Yang Jou (IEEE Trans. Very Large Scale Integr. Syst., 2009)

FSM-Based Formal Compliance Verification of Interface Protocols. - Che-Hua Shih; Ya-Ching Yang; Chia-Chih Yen; Juinn-Dar Huang; Jing-Yang Jou (J. Inf. Sci. Eng., 2010)

Equivalence checking of scheduling with speculative code transformations in high-level synthesis. - Chi-Hui Lee; Che-Hua Shih; Juinn-Dar Huang; Jing-Yang Jou (ASP-DAC, 2011)

Embedding Hierarchical Signal to Siamese Network for Fast Name Rectification. - Yi-An Chen; Gung-Yu Pan; Che-Hua Shih; Yen-Chin Liao; Chia-Chih Yen; Hsie-Chia Chang (DATE, 2020)