ESD protection circuit for high-voltage CMOS ICs with improved immunity against transient-induced latchup. - Ming-Dou Ker; Che-Lun Hsu; Wen-Yi Chen (ISCAS, 2010)

PARR: Pin-Access Planning and Regular Routing for Self-Aligned Double Patterning. - Xiaoqing Xu; Bei Yu 001; Jhih-Rong Gao; Che-Lun Hsu; David Z. Pan (ACM Trans. Design Autom. Electr. Syst., 2016)

Layout-dependent aging mitigation for critical path timing. - Che-Lun Hsu; Shaofeng Guo; Yibo Lin; Xiaoqing Xu; Meng Li 004; Runsheng Wang; Ru Huang 001; David Z. Pan (ASP-DAC, 2018)