Optimal design of Ge-dot photoMOSFETs for highly-integrated monolithic Si photonics. - Ming-Hao Kuo; Meng Chun Lee; Che-Wei Tien; Wei-Ting Lai; Pei-Wen Li (OFC, 2017)

A Digital Phase-Locked Loop With Background Supply Voltage Sensitivity Minimization. - Che-Wei Tien; Shen-Iuan Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A PVT-Tolerant Injection-Locked Clock Multiplier With a Frequency Calibrator Using a Delay Time Detector. - Che-Wei Tien; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2019)