An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory. - Meng-Fan Chang; Shin-Jang Shen; Chia-Chi Liu; Che-Wei Wu; Yu-Fan Lin; Shang-Chi Wu; Chia-En Huang; Han-Chao Lai; Ya-Chin King; Chorng-Jung Lin; Hung-Jen Liao; Yu-Der Chih; et al. (ISSCC, 2011)

A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability. - Shyh-Shyuan Sheu; Meng-Fan Chang; Ku-Feng Lin; Che-Wei Wu; Yu-Sheng Chen; Pi-Feng Chiu; Chia-Chen Kuo; Yih-Shan Yang; Pei-Chia Chiang; Wen-Pin Lin; Che-He Lin; Heng-Yuan Lee; et al. (ISSCC, 2011)

A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time. - Meng-Fan Chang; Che-Wei Wu; Chia-Chen Kuo; Shin-Jang Shen; Ku-Feng Lin; Shu-Meng Yang; Ya-Chin King; Chorng-Jung Lin; Yu-Der Chih (ISSCC, 2012)

Low Store Energy, Low VDDmin, 8T2R Nonvolatile Latch and SRAM With Vertical-Stacked Resistive Memory (Memristor) Devices for Low Power Mobile Applications. - Pi-Feng Chiu; Meng-Fan Chang; Che-Wei Wu; Ching-Hao Chuang; Shyh-Shyuan Sheu; Yu-Sheng Chen; Ming-Jinn Tsai (IEEE J. Solid State Circuits, 2012)

Degradation algorithm of compressive sensing for integer DCT with application to H. 264/AVC. - Shiunn-Jang Chern; Che-Wei Wu; Ching-Tang Hsieh (ISPACS, 2013)

A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes. - Meng-Fan Chang; Shyh-Shyuan Sheu; Ku-Feng Lin; Che-Wei Wu; Chia-Chen Kuo; Pi-Feng Chiu; Yih-Shan Yang; Yu-Sheng Chen; Heng-Yuan Lee; Chen-Hsin Lien; Frederick T. Chen; Keng-Li Su; et al. (IEEE J. Solid State Circuits, 2013)

An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory. - Meng-Fan Chang; Shin-Jang Shen; Chia-Chi Liu; Che-Wei Wu; Yu-Fan Lin; Ya-Chin King; Chorng-Jung Lin; Hung-Jen Liao; Yu-Der Chih; Hiroyuki Yamauchi (IEEE J. Solid State Circuits, 2013)

A Low-Voltage Bulk-Drain-Driven Read Scheme for Sub-0.5 V 4 Mb 65 nm Logic-Process Compatible Embedded Resistive RAM (ReRAM) Macro. - Meng-Fan Chang; Che-Wei Wu; Chia-Chen Kuo; Shin-Jang Shen; Sue-Meng Yang; Ku-Feng Lin; Wen-Chao Shen; Ya-Chin King; Chorng-Jung Lin; Yu-Der Chih (IEEE J. Solid State Circuits, 2013)

A low-power subthreshold-to-superthreshold level-shifter for sub-0.5V embedded resistive RAM (ReRAM) macro in ultra low-voltage chips. - Meng-Fan Chang; Che-Wei Wu; Jui-Yu Hung; Ya-Chin King; Chomg-Jung Lin; Mon-Shu Ho; Chia-Cheng Kuo; Shyh-Shyuan Sheu (APCCAS, 2014)

Deep Learning-Enabled Swallowing Monitoring and Postoperative Recovery Biosensing System. - Chih-Ning Tsai; Pei-Wen Yang; Tzu-Yen Huang; Jung-Chih Chen; Hsin-Yi Tseng; Che-Wei Wu; Amrit Sarmah; Tzu-En Lin (CoRR, 2023)