An FPGA-based re-configurable functional tester for memory chips. - Jing-Reng Huang; Chee-Kian Ong; Kwang-Ting Cheng; Cheng-Wen Wu (Asian Test Symposium, 2000)

A BIST Scheme for On-Chip ADC and DAC Testing. - Jiun-Lang Huang; Chee-Kian Ong; Kwang-Ting Cheng (DATE, 2000)

Characterization of a Pseudo-Random Testing Technique for Analog and Mixed-Signal Built-in-Self-Test. - Jan Arild Tofte; Chee-Kian Ong; Jiun-Lang Huang; Kwang-Ting (Tim) Cheng (VTS, 2000)

Self-Testing Second-Order Delta-Sigma Modulators Using Digital Stimulus. - Chee-Kian Ong; Kwang-Ting (Tim) Cheng (VTS, 2002)

Delta-sigma modulator based mixed-signal BIST architecture for SoC. - Chee-Kian Ong; Kwang-Ting (Tim) Cheng; Li-C. Wang (ASP-DAC, 2003)

Jitter spectral extraction for multi-gigahertz signal. - Chee-Kian Ong; Dongwoo Hong; Kwang-Ting Cheng; Li-C. Wang (ASP-DAC, 2004)

Random Jitter Extraction Technique in a Multi-Gigahertz Signal. - Chee-Kian Ong; Dongwoo Hong; Kwang-Ting Cheng; Li-C. Wang (DATE, 2004)

BER Estimation for Serial Links Based on Jitter Spectrum and Clock Recovery Characteristics. - Dongwoo Hong; Chee-Kian Ong; Kwang-Ting (Tim) Cheng (ITC, 2004)

A Scalable On-Chip Jitter Extraction Technique. - Chee-Kian Ong; Dongwoo Hong; Kwang-Ting Cheng; Li-C. Wang (VTS, 2004)

A new sigma-delta modulator architecture for testing using digital stimulus. - Chee-Kian Ong; Kwang-Ting Cheng; Li-C. Wang (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

Bit-Error-Rate Estimation for High-Speed Serial Links. - Dongwoo Hong; Chee-Kian Ong; Kwang-Ting (Tim) Cheng (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

A Clock-Less Jitter Spectral Analysis Technique. - Chee-Kian Ong; Dongwoo Hong; Kwang-Ting Cheng; Li-C. Wang (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)