Real-Time Configuration for Fault-Tolerant VLSI Array Processors. - Sun-Yuan Kung; Chih-Wei Jim Chang; Chein-Wei Jen (RTSS, 1986)

Two-level pipeline design for image resampling. - Chein-Wei Jen; Chi-Min Liu (ICASSP, 1989)

Multi-dimensional parallel computing structures for regular iterative algorithms. - Chein-Wei Jen; Ding-Ming Kwai (Integr., 1989)

Recursive algorithms for AR spectral estimation and their array realizations. - Chi-Min Liu; Chein-Wei Jen (ASAP, 1990)

Parallel adaptive algorithm for moving target indicator and its VLSI array realization. - Chi-Min Liu; Bor-Shyong Yang; Chein-Wei Jen (ICASSP, 1990)

A high-level synthesizer for VLSI array architectures dedicated to digital signal processing. - Tung-Hao Huang; Chi-Min Liu; Chein-Wei Jen (ICASSP, 1991)

A memory-based approach to design and implement systolic arrays for DFT and DCT. - Jiun-In Guo; Chi-Min Liu; Chein-Wei Jen (ICASSP, 1992)

Efficient synthesis and high-speed implementation of look-ahead recursive filters. - Chien-Piao Lan; Shih-Chieh Wen; Chein-Wei Jen (ICASSP, 1992)

Design of Two-Level Pipelined Systolic Array and its Application to Image. - Chein-Wei Jen; Chi-Min Liu (J. Circuits Syst. Comput., 1992)

Data Flow Representation of Iterative Algorithms for Systolic Arrays. - Chein-Wei Jen; Ding-Ming Kwai (IEEE Trans. Computers, 1992)

A parallel adaptive algorithm for moving target detection and its VLSI array realization. - Chi-Min Liu; Chein-Wei Jen (IEEE Trans. Signal Process., 1992)

A CORDIC-based VLSI Array for Computing 2-D Discrete Hartley Transform. - Jiun-In Guo; Chi-Min Liu; Chein-Wei Jen (ISCAS, 1993)

A Multi-phase Shared Bus Structure for the Fast Fourier Transform. - Yu-Sheng Lin; Jiun-In Guo; C. Bernard Shung; Chein-Wei Jen (ISCAS, 1993)

A High Throughput Systolic Design for QR Algorithm. - Jiann-Jenn Wang; Chein-Wei Jen (ISCAS, 1993)

A New Array Architecture for Prime-Length Discrete Cosine Transform. - Jiun-In Guo; Chi-Min Liu; Chein-Wei Jen (IEEE Trans. Signal Process., 1993)

Binary partition algorithms and VLSI architectures for median and rank order filtering. - Chamg Long Lee; Chein-Wei Jen (IEEE Trans. Signal Process., 1993)

A novel VLSI array design for the discrete Hartley transform using cyclic convolution. - Jiun-In Guo; Chi-Min Liu; Chein-Wei Jen (ICASSP (2), 1994)

A General Approach to Design VLSI Arrays for the Multi-dimensional Discrete Hartley Transform. - Jiun-In Guo; Chi-Min Liu; Chein-Wei Jen (ISCAS, 1994)

A motion detection scheme for motion adaptive pro-scan conversion. - Shifan Chang; Chein-Wei Jen; Charng Long Lee (Signal Process. Image Commun., 1994)

Scalable array architecture design for full search block matching. - Shifan Chang; Juin-Haur Hwang; Chein-Wei Jen (IEEE Trans. Circuits Syst. Video Technol., 1995)

A programmable concurrent video signal processor. - Chih-Chin Chen; Chein-Wei Jen (ICIP (2), 1996)

VASS - A VLSI array system synthesizer. - Jinn-Wang Yeh; Wen-Jiunn Cheng; Chein-Wei Jen (J. VLSI Signal Process., 1996)

An Architecture of Full-Search Block Matching for Minimum Memory Bandwidth Requirement. - Jen-Chien Tuan; Chein-Wei Jen (Great Lakes Symposium on VLSI, 1998)

Low power FIR filter realization with differential coefficients and input. - Tian-Sheuan Chang; Chein-Wei Jen (ICASSP, 1998)

Bus buffer modeling and optimization in video processing IP. - Kun-Bin Lee; Chia-Hsing Lin; Chein-Wei Jen (ICECS, 1999)

On-Line Polygon Refining Using a Low Computation Subdivision Algorithm. - Yuan-Chung Lee; Chein-Wei Jen (GMP, 2000)

A high performance carry-save to signed-digit recoder for fused addition-multiplication. - Wen-Chang Yeh; Chein-Wei Jen (ICASSP, 2000)

A new hardware design and FPGA implementation for Internet routing towards IP over WDM and terabit routers. - Ilion Yi-Liang Hsiao; Chein-Wei Jen (ISCAS, 2000)

Deferred lighting: a computation-efficient approach for real-time 3-D graphics. - Bor-Sung Liang; Wen-Chang Yeh; Yuan-Chung Lee; Chein-Wei Jen (ISCAS, 2000)

Motion estimation using on-line arithmetic. - Ching-Long Su; Chein-Wei Jen (ISCAS, 2000)

High-Speed Booth Encoded Parallel Multiplier Design. - Wen-Chang Yeh; Chein-Wei Jen (IEEE Trans. Computers, 2000)

Computation-effective 3-D graphics rendering architecture for embedded multimedia system. - Bor-Sung Liang; Chein-Wei Jen (IEEE Trans. Consumer Electron., 2000)

A simple processor core design for DCT/IDCT. - Tian-Sheuan Chang; Chin-Sheng Kung; Chein-Wei Jen (IEEE Trans. Circuits Syst. Video Technol., 2000)

Power modeling and low-power design of content addressable memories. - Ilion Yi-Liang Hsiao; Ding-Hao Wang; Chein-Wei Jen (ISCAS (4), 2001)

Arbitrarily scalable edge-preserving interpolation for 3-D graphics and video resizing. - Yuan-Chung Lee; Chein-Wei Jen (ISCAS (2), 2001)

An efficient 2-D DWT architecture via resource cycling. - Tay-Jyi Lin; Chein-Wei Jen (ISCAS (4), 2001)

Improved quadratic normal vector interpolation for realistic shading. - Yuan-Chung Lee; Chein-Wei Jen (Vis. Comput., 2001)

A new group distributed arithmetic design for the one dimensional discrete Fourier transform. - Hun-Chen Chen; Jiun-In Guo; Chein-Wei Jen (ISCAS (1), 2002)

High-speed memory-saving architecture for the embedded block coding in JPEG2000. - Yun-Tai Hsiao; Hung-Der Lin; Kun-Bin Lee; Chein-Wei Jen (ISCAS (5), 2002)

CASCADE - configurable and scalable DSP environment. - Tay-Jyi Lin; Chein-Wei Jen (ISCAS (4), 2002)

On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture. - Jen-Chieh Tuan; Tian-Sheuan Chang; Chein-Wei Jen (IEEE Trans. Circuits Syst. Video Technol., 2002)

Index rendering: hardware-efficient architecture for 3-D graphics in multimedia system. - Bor-Sung Liang; Yuan-Chung Lee; Wen-Chang Yeh; Chein-Wei Jen (IEEE Trans. Multim., 2002)

An Efficient VLIW DSP Architecture for Baseband Processing. - Tay-Jyi Lin; Chin-Chi Chang; Chen-Chia Lee; Chein-Wei Jen (ICCD, 2003)

Performance evaluation of ring-structure register file in multimedia applications. - Tay-Jyi Lin; Chin-Chi Chang; Tsung-Hsun Yang; Yu-Ming Chang; Chien-Hung Lin; Chen-Chia Lee; Hung-Yueh Lin; Chein-Wei Jen (ICME, 2003)

Coefficient optimization for area-effective multiplier-less FIR filters. - Tay-Jyi Lin; Tsung-Hsun Yang; Chein-Wei Jen (ICME, 2003)

A memory efficient realization of cyclic convolution and its application to discrete cosine transform. - Hun-Chen Chen; Jiun-In Guo; Chein-Wei Jen (ISCAS (4), 2003)

Area-effective FIR filter design for multiplier-less implementation. - Tay-Jyi Lin; Tsung-Hsun Yang; Chein-Wei Jen (ISCAS (5), 2003)

Generalized Earliest-First Fast Addition Algorithm. - Wen-Chang Yeh; Chein-Wei Jen (IEEE Trans. Computers, 2003)

High-speed and low-power split-radix FFT. - Wen-Chang Yeh; Chein-Wei Jen (IEEE Trans. Signal Process., 2003)

Edge-preserving texture filtering for real-time rendering. - Yuan-Chung Lee; Chein-Wei Jen (Vis. Comput., 2003)

A bandwidth and memory efficient MPEG-4 shape encoder. - Kun-Bin Lee; Nelson Yen-Chung Chang; Hao-Yun Chin; Hui-Cheng Hsu; Chein-Wei Jen (ASP-DAC, 2004)

A compact DSP core with static floating-point unit & its microcode generation. - Tay-Jyi Lin; Hung-Yueh Lin; Chie-Min Chao; Chih-Wei Liu; Chein-Wei Jen (ACM Great Lakes Symposium on VLSI, 2004)

Trace-path analysis and performance estimation for multimedia application in embedded system. - Nelson Yen-Chung Chang; Kun-Bin Lee; Chein-Wei Jen (ISCAS (2), 2004)

QME: an efficient subsampling-based block matching algorithm for motion estimation. - Kun-Bin Lee; Hao-Yun Chin; Hui-Cheng Hsu; Chein-Wei Jen (ISCAS (2), 2004)

A cost-effective MPEG-4 shape-adaptive DCT with auto-aligned transpose memory organization. - Kun-Bin Lee; Hui-Cheng Hsu; Chein-Wei Jen (ISCAS (2), 2004)

A fast dual symbol context-based arithmetic coding for MPEG-4 shape coding. - Kun-Bin Lee; Jih-Yiing Lin; Chein-Wei Jen (ISCAS (2), 2004)

Static floating-point unit with implicit exponent tracking for embedded DSP. - Hung-Yueh Lin; Tay-Jyi Lin; Chie-Min Chao; Yen-Chin Liao; Chih-Wei Liu; Chein-Wei Jen (ISCAS (2), 2004)

Optimal frame memory and data transfer scheme for MPEG-4 shape coding. - Kun-Bin Lee; Hao-Yun Chin; Nelson Yen-Chung Chang; Hui-Cheng Hsu; Chein-Wei Jen (IEEE Trans. Consumer Electron., 2004)

A unified processor architecture for RISC & VLIW DSP. - Tay-Jyi Lin; Chie-Min Chao; Chia-Hsien Liu; Pi-Chen Hsiao; Shin-Kai Chen; Li-Chun Lin; Chih-Wei Liu; Chein-Wei Jen (ACM Great Lakes Symposium on VLSI, 2005)

Architecture for area-efficient 2-D transform in H.264/AVC. - Yu-Ting Kuo; Tay-Jyi Lin; Chih-Wei Liu; Chein-Wei Jen (ICME, 2005)

Pipelining technique for energy-aware datapaths. - Wei-Sheng Huang; Tay-Jyi Lin; Shih-Hao Ou; Chih-Wei Liu; Chein-Wei Jen (ISCAS (2), 2005)

Hierarchical instruction encoding for VLIW digital signal processors. - Chia-Hsien Liu; Tay-Jyi Lin; Chie-Min Chao; Pi-Chen Hsiao; Li-Chun Lin; Shin-Kai Chen; Chao-Wei Huang; Chih-Wei Liu; Chein-Wei Jen (ISCAS (4), 2005)

The Long Length DHT Design with a New Hardware Efficient Distributed Arithmetic Approach and Cyclic Preserving Partitioning. - Hun-Chen Chen; Tian-Sheuan Chang; Jiun-In Guo; Chein-Wei Jen (IEICE Trans. Electron., 2005)

A memory-efficient realization of cyclic convolution and its application to discrete cosine transform. - Hun-Chen Chen; Jiun-In Guo; Tian-Sheuan Chang; Chein-Wei Jen (IEEE Trans. Circuits Syst. Video Technol., 2005)

A multisymbol context-based arithmetic coding architecture for MPEG-4 shape coding. - Kun-Bin Lee; Jih-Yiing Lin; Chein-Wei Jen (IEEE Trans. Circuits Syst. Video Technol., 2005)

An Efficient Quality-Aware Memory Controller for Multimedia Platform SoC. - Kun-Bin Lee; Tzu-Chieh Lin; Chein-Wei Jen (IEEE Trans. Circuits Syst. Video Technol., 2005)

A 52mW 1200MIPS compact DSP for multi-core media SoC. - Shih-Hao Ou; Tay-Jyi Lin; Chao-Wei Huang; Yu-Ting Kuo; Chie-Min Chao; Chih-Wei Liu; Chein-Wei Jen (ASP-DAC, 2006)

PAC DSP Core and Application Processors. - David Chih-Wei Chang; I-Tao Liao; Jenq Kuen Lee; Wen-Feng Chen; Shau-Yin Tseng; Chein-Wei Jen (ICME, 2006)

Programmable FIR filter with adder-based computing engine. - Yu-Ting Kuo; Tay-Jyi Lin; Yi Cho; Chih-Wei Liu; Chein-Wei Jen (ISCAS, 2006)

Latency-Tolerant Virtual Cluster Architecture for VLIW DSP. - Pi-Chen Hsiao; Tay-Jyi Lin; Chih-Wei Liu; Chein-Wei Jen (ISCAS, 2007)