A timing failure tolerance design with in-field simultaneous error detection and correction. - Ziyi Hao; Xiaoyan Xiang; Chen Chen 058; Jianyi Meng (ASICON, 2015)

An energy-efficient microprocessor using multilevel error correction for timing error tolerance. - Sheng Wang 005; Xiaoyan Xiang; Chen Chen 058; Jianyi Meng (ASICON, 2015)

A near threshold error resilient processor based on dynamic timing error prediction and within-a-cycle timing error correction. - Tao-Tao Zhu; Xiaoyan Xiang; Chen Chen 058; Jianyi Meng (ASICON, 2015)

Value locality based storage compression memory architecture for ECG sensor node. - Chaojun Zhao; Chen Chen 058; Zhijian Chen; Jianyi Meng (Sci. China Inf. Sci., 2016)

EDSU: Error detection and sampling unified flip-flop with ultra-low overhead. - Ziyi Hao; Xiaoyan Xiang; Chen Chen 058; Jianyi Meng; Yong Ding 003; Xiaolang Yan (IEICE Electron. Express, 2016)

TBCT: Time-Borrowing and Clock Token based error correction and its application in microprocessor. - Zhenqiang Yong; Xiaoyan Xiang; Jianyi Meng; Chen Chen 058 (IEICE Electron. Express, 2016)

A light-weight energy-efficient resilient circuit for variation tolerance. - Xiaopei Chen; Sheng Wang 005; Xiaoyan Xiang; Chen Chen 058; Jianyi Meng (ASICON, 2017)

A new error masking flip-flop with one cycle correction penalty. - Zhenqiang Yong; Xiaoyan Xiang; Chen Chen 058; Jianyi Meng (ASICON, 2017)

A metastability-immune error-resilient flip-flop for near-threshold variation-tolerant designs. - Sheng Wang 005; Chen Chen 058; Xiaoyan Xiang; Jianyi Meng (IEICE Electron. Express, 2017)

SGERC: a self-gated timing error resilient cluster of sequential cells for wide-voltage processor. - Tao-Tao Zhu; Xiaoyan Xiang; Chen Chen 058; Jianyi Meng (IEICE Electron. Express, 2017)

A Variation-Tolerant Near-Threshold Processor With Instruction-Level Error Correction. - Sheng Wang 005; Chen Chen 058; Xiaoyan Xiang; Jian-Yi Meng (IEEE Trans. Very Large Scale Integr. Syst., 2017)

An Energy-Efficient and Wide-Range Voltage Level Shifter With Dual Current Mirror. - Zhenqiang Yong; Xiaoyan Xiang; Chen Chen 058; Jianyi Meng (IEEE Trans. Very Large Scale Integr. Syst., 2017)

An effectiveness-oriented greedy heuristic for padding short paths in ultra-low supply voltage designs. - Yan He; Jianyi Meng; Zhijian Chen; Xiaoyan Xiang; Chen Chen 058 (IEICE Electron. Express, 2018)

Xuantie-910: Innovating Cloud and Edge Computing by RISC-V. - Chen Chen 058; Xiaoyan Xiang; Chang Liu 021; Yunhai Shang; Ren Guo; Dongqi Liu 003; Yimin Lu; Ziyi Hao; Jiahui Luo; Zhijian Chen; Chunqiang Li; Yu Pu; et al. (Hot Chips Symposium, 2020)

Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial Product. - Chen Chen 058; Xiaoyan Xiang; Chang Liu 021; Yunhai Shang; Ren Guo; Dongqi Liu 003; Yimin Lu; Ziyi Hao; Jiahui Luo; Zhijian Chen; Chunqiang Li; Yu Pu; et al. (ISCA, 2020)

Enhancing RISC-V Vector Extension for Efficient Application of Post-Quantum Cryptography. - Yifan Zhao 007; Honglin Kuang; Yi Sun; Zhen Yang; Chen Chen 058; Jianyi Meng; Jun Han 003 (ASAP, 2023)