Equivalent Capacitance Guided Dummy Fill Insertion for Timing and Manufacturability. - Sheng-Jung Yu; Chen-Chien Kao; Chia-Han Huang; Iris Hui-Ru Jiang (ASP-DAC, 2020)

Iterative Receiver with a Lattice-Reduction-Aided MIMO Detector for IEEE 802.11ax. - Yao-Pin Wang; Chi-Chih Wen; Chen-Chien Kao; Chung-Jung Huang; Der-Zheng Liu; Chia-Hsiang Yang (GLOBECOM, 2020)

A 1.96 Gb/s Massive MU-MIMO Detector for Next-Generation Cellular Systems. - Chi-Chih Wen; Yu-Chi Lee; Yi-Chung Wu; Chen-Chien Kao; Chia-Hsiang Yang (VLSI Circuits, 2020)

Hardware Acceleration in Large-Scale Tensor Decomposition for Neural Network Compression. - Chen-Chien Kao; Yi-Yen Hsieh; Chao-Hung Chen; Chia-Hsiang Yang (MWSCAS, 2022)

Hybrid Precoding Baseband Processor for 64 × 64 Millimeter Wave MIMO Systems. - Chen-Chien Kao; Chiao-En Chen; Chia-Hsiang Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

M3XU: Achieving High-Precision and Complex Matrix Multiplication with Low-Precision MXUs. - Dongho Ha; Yunan Zhang; Chen-Chien Kao; Christopher J. Hughes; Won Woo Ro; Hung-Wei Tseng 001 (SC, 2024)