Design strategy of localized halo profile for achieving sub-50 nm bulk MOSFET. - Chun-Hsing Shih; Yi-Min Chen; Chen-Hsin Lien (Microelectron. Reliab., 2004)

A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability. - Shyh-Shyuan Sheu; Meng-Fan Chang; Ku-Feng Lin; Che-Wei Wu; Yu-Sheng Chen; Pi-Feng Chiu; Chia-Chen Kuo; Yih-Shan Yang; Pei-Chia Chiang; Wen-Pin Lin; Che-He Lin; Heng-Yuan Lee; et al. (ISSCC, 2011)

A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes. - Meng-Fan Chang; Shyh-Shyuan Sheu; Ku-Feng Lin; Che-Wei Wu; Chia-Chen Kuo; Pi-Feng Chiu; Yih-Shan Yang; Yu-Sheng Chen; Heng-Yuan Lee; Chen-Hsin Lien; Frederick T. Chen; Keng-Li Su; et al. (IEEE J. Solid State Circuits, 2013)

Robust ESD self-protected LDNMOSFET by an enhanced displacement-current triggering. - Tzu-Cheng Kao; Chen-Hsin Lien; Chien-Wei Chiu; Jian-Hsing Lee; Yen-Hsiang Lo; Chung-Yu Hung; Tsung-Yi Huang; Hung-Der Su (IRPS, 2015)

Enhanced CDM-robustness for the packaged IC with the extra bonding wire to the die-attach plate. - Tzu-Cheng Kao; Jian-Hsing Lee; Chen-Hsin Lien; Chih-Hsien Wang; Kuang-Cheng Tai; Hung-Der Su (IRPS, 2015)

Reliability impacts of high-speed 3-bit/cell Schottky barrier nanowire charge-trapping memories. - Wei Chang; Chun-Hsing Shih; Yan-Xiang Luo; Wen-Fa Wu; Chen-Hsin Lien (Microelectron. Reliab., 2015)