Random pattern testable logic synthesis. - Chen-Huan Chiang; Sandeep K. Gupta 001 (ICCAD, 1994)

BIST TPG for faults in system backplanes. - Chen-Huan Chiang; Sandeep K. Gupta 001 (ICCAD, 1997)

BIST TPGs for Faults in Board Level Interconnect via Boundary Scan. - Chen-Huan Chiang; Sandeep K. Gupta 001 (VTS, 1997)

BIST TPG for Combinational Cluster (Glue Logic) Interconnect Testing at Board Level. - Chen-Huan Chiang; Sandeep K. Gupta 001 (Asian Test Symposium, 1998)

BIST TPG for SRAM cluster interconnect testing at board level. - Chen-Huan Chiang; Sandeep K. Gupta 001 (Asian Test Symposium, 2000)

End-to-end testing for boards and systems using boundary scan. - Robert W. Barr; Chen-Huan Chiang; Edward L. Wallace (ITC, 2000)

BIST TPG for Combinational Cluster Interconnect Testing at Board Level. - Chen-Huan Chiang; Sandeep K. Gupta 001 (J. Electron. Test., 2000)

A Novel Fault Injection Method for System Verification Based on FPGA Boundary Scan Architectur. - Tapan J. Chakraborty; Chen-Huan Chiang (ITC, 2002)

Testing and Remote Field Update of Distributed Base Stations in a Wireless Network. - Chen-Huan Chiang; Paul J. Wheatley; Kenneth Y. Ho; Ken L. Cheung (ITC, 2004)

A practical approach to comprehensive system test & debug using boundary scan based test architecture. - Tapan J. Chakraborty; Chen-Huan Chiang; Bradford G. Van Treuren (ITC, 2007)

FPGA Prototyping of a Scan Based System-On-Chip Design. - Brendan Mullane; Chen-Huan Chiang; Michael Higgins; Ciaran MacNamee; Tapan J. Chakraborty; Thomas B. Cook (ReCoSoC, 2007)

A New Language Approach for IJTAG. - Michele Portolan; Suresh Goyal; Bradford G. Van Treuren; Chen-Huan Chiang; Tapan J. Chakraborty; Thomas B. Cook (ITC, 2008)

Problems Using Boundary-Scan for Memory Cluster Tests. - Bradford G. Van Treuren; Chen-Huan Chiang; Kenneth Honaker (ITC, 2008)

A Common Language Framework for Next-Generation Embedded Testing. - Michele Portolan; Suresh Goyal; Bradford G. Van Treuren; Chen-Huan Chiang; Tapan J. Chakraborty; Thomas B. Cook (IEEE Des. Test Comput., 2010)

Design for Bit Error Rate estimation of high speed serial links. - Ujjwal Guin; Chen-Huan Chiang (VTS, 2011)