Automatic Functional Test Program Generation for Microprocessors. - Chen-Shang Lin; Hong-Fa Ho (DAC, 1988)

VVDS: A Verification/Diagnosis System for VHDL. - Heh-Tyan Liaw; K.-T. Tran; Chen-Shang Lin (DAC, 1989)

Efficient Automatic Diagnosis of Digital Circuits. - Heh-Tyan Liaw; Jia-Horng Tsaih; Chen-Shang Lin (ICCAD, 1990)

Automatic Synthesis of Asynchronous Circuits. - Kuan-Jen Lin; Chen-Shang Lin (DAC, 1991)

On the verification of state-coding in STGs. - Kuan-Jen Lin; Chen-Shang Lin (ICCAD, 1992)

On the OBDD-Representation of General Boolean Functions. - Heh-Tyan Liaw; Chen-Shang Lin (IEEE Trans. Computers, 1992)

Direct Synthesis of Hazard-Free Asynchronous Circuits from STGs Based on Lock Relation and BG-Decomposition Approach. - Kuan-Jen Lin; Jih-Wen Kuo; Chen-Shang Lin (EDAC-ETC-EUROASIC, 1994)

HyHOPE: a fast fault simulator with efficient simulation of hypertrophic faults. - Chen-Pin Kung; Chen-Shang Lin (ICCAD, 1994)

A Test-Clock Reduction Method for Scan-Designed Circuits. - Jau-Shien Chang; Chen-Shang Lin (ITC, 1994)

Fast fault simulation for BIST applications. - Chen-Pin Kung; Chun-Jieh Huang; Chen-Shang Lin (Asian Test Symposium, 1995)

Test set compaction for combinational circuits. - Jau-Shien Chang; Chen-Shang Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Parallel sequence fault simulation for synchronous sequential circuits. - Chen-Pin Kung; Chen-Shang Lin (J. Electron. Test., 1996)

Synthesis of Hazard-Free Asynchronous Circuits Based on Characteristic Graph. - Kuan-Jen Lin; Chi-Wen Kuo; Chen-Shang Lin (IEEE Trans. Computers, 1997)