A 387.6fs Integrated Jitter and -80dBc Reference Spurs Ring based PLL with Track- and-Hold Charge Pump and Automatic Loop Gain Control in 7nm FinFET CMOS. - Chen-Ting Ko; Ting-Kuei Kuan; Ruei-Pin Shen; Chih-Hsien Chang; Kenny Hsieh; Mark Chen 001 (VLSI Circuits, 2019)

A 7-nm FinFET CMOS PLL With 388-fs Jitter and -80-dBc Reference Spur Featuring a Track-and-Hold Charge Pump and Automatic Loop Gain Control. - Chen-Ting Ko; Ting-Kuei Kuan; Ruei-Pin Shen; Chih-Hsien Chang (IEEE J. Solid State Circuits, 2020)