Configuration approaches to improve computing efficiency of coarse-grained reconfigurable multimedia processor. - Chen Yang 005; Leibo Liu; Yansheng Wang; Shouyi Yin; Peng Cao 002; Shaojun Wei (FPL, 2014)

Cost-Effective Memory Architecture to Achieve Flexible Configuration and Efficient Data Transmission for Coarse-Grained Reconfigurable Array (Abstract Only). - Chen Yang 005; Leibo Liu; Shouyi Yin; Shaojun Wei (FPGA, 2015)

Configuration Approaches to Enhance Computing Efficiency of Coarse-Grained Reconfigurable Array. - Chen Yang 005; Leibo Liu; Yansheng Wang; Shouyi Yin; Peng Cao 002; Shaojun Wei (J. Circuits Syst. Comput., 2015)

Data cache prefetching via context directed pattern matching for coarse-grained reconfigurable arrays. - Chen Yang 005; Leibo Liu; Shouyi Yin; Shaojun Wei (DAC, 2016)

CIACP: A Correlation- and Iteration- Aware Cache Partitioning Mechanism to Improve Performance of Multiple Coarse-Grained Reconfigurable Arrays. - Chen Yang 005; Leibo Liu; Kai Luo; Shouyi Yin; Shaojun Wei (IEEE Trans. Parallel Distributed Syst., 2017)

CDPM: Context-Directed Pattern Matching Prefetching to Improve Coarse-Grained Reconfigurable Array Performance. - Leibo Liu; Chen Yang 005; Shouyi Yin; Shaojun Wei (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

HReA: An Energy-Efficient Embedded Dynamically Reconfigurable Fabric for 13-Dwarfs Processing. - Leibo Liu; Zhaoshi Li; Chen Yang 005; Chenchen Deng; Shouyi Yin; Shaojun Wei (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

CCP: Configuration Context based Prefetching to Improve Coarse-Grained Reconfigurable Array Performance. - Chen Yang 005; Jia Hou; Yizhou Wang 004; Qi Zhou; Li Geng (ICECS, 2019)

A Fully Quantitative Scheme With Fine-grained Tuning Method For Lightweight CNN Acceleration. - Chen Yang 005; Bowen Li; Yizhou Wang 004 (ICECS, 2019)

WRA: A 2.2-to-6.3 TOPS Highly Unified Dynamically Reconfigurable Accelerator Using a Novel Winograd Decomposition Algorithm for Convolutional Neural Networks. - Chen Yang 005; Yizhou Wang 004; Xiaoli Wang; Li Geng (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

CRP: Context-directed Replacement Policy to Improve Cache Performance for Coarse-Grained Reconfigurable Arrays. - Chen Yang 005; Jia Hou; Yizhou Wang 004; Li Geng (ICECS, 2020)

FPGA-Based Hardware Accelerator for Leveled Ring-LWE Fully Homomorphic Encryption. - Yang Su 003; Bailong Yang; Chen Yang 005; Luogeng Tian (IEEE Access, 2020)

A Stride-Based Convolution Decomposition Method to Stretch CNN Acceleration Algorithms for Efficient and Flexible Hardware Implementation. - Chen Yang 005; Yizhou Wang 004; Xiaoli Wang; Li Geng (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

A Lightweight Full Homomorphic Encryption Scheme on Fully-connected Layer for CNN Hardware Accelerator achieving Security Inference. - Chen Yang 005; Zepeng Yang; Jia Hou; Yang Su 003 (ICECS, 2021)

High-flexible hardware and instruction of composite Galois field multiplication targeted at symmetric crypto processor. - Yang Su 003; Bai-Long Yang; Chen Yang 005; Jing-Yuan He (J. Ambient Intell. Humaniz. Comput., 2021)

UL-CNN: An Ultra-Lightweight Convolutional Neural Network Aiming at Flash-Based Computing-In-Memory Architecture for Pedestrian Recognition. - Chen Yang 005; Jingyu Zhang; Qi Chen; Yi Xu; Cimang Lu (J. Circuits Syst. Comput., 2021)

A Hardware Architecture of Feature Extraction for Real-Time Visual SLAM. - Jialin Li; Liangji Zhang; Xuewei Shen; Yifan Gong 005; Ying Lei; Chen Yang 005; Li Geng (IECON, 2022)

SDF-SLAM: A Deep Learning Based Highly Accurate SLAM Using Monocular Camera Aiming at Indoor Map Reconstruction With Semantic and Depth Fusion. - Chen Yang 005; Qi Chen; Yaoyao Yang; Jingyu Zhang; Minshun Wu; Kuizhi Mei (IEEE Access, 2022)

RNA: A Flexible and Efficient Accelerator Based on Dynamically Reconfigurable Computing for Multiple Convolutional Neural Networks. - Chen Yang 005; Jia Hou; Yizhou Wang 004; Haibo Zhang; Xiaoli Wang; Li Geng (J. Circuits Syst. Comput., 2022)

ReMCA: A Reconfigurable Multi-Core Architecture for Full RNS Variant of BFV Homomorphic Evaluation. - Yang Su 003; Bai-Long Yang; Chen Yang 005; Songyin Zhao (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Highly Unified Reconfigurable Multicore Architecture to Speed Up NTT/INTT for Homomorphic Polynomial Multiplication. - Yang Su 003; Bai-Long Yang; Chen Yang 005; Zepeng Yang; Yi-Wei Liu (IEEE Trans. Very Large Scale Integr. Syst., 2022)

A Sparse CNN Accelerator for Eliminating Redundant Computations in Intra- and Inter-Convolutional/Pooling Layers. - Chen Yang 005; Yishuo Meng; Kaibo Huo; Jiawei Xi; Kuizhi Mei (IEEE Trans. Very Large Scale Integr. Syst., 2022)

An Efficient Hardware Implementation of Dilated Convolution Using a Novel Channel-Equivalent Decomposition Method. - Yuheng Xia; Yishuo Meng; Siwei Xiang; Jianfei Wang 003; Chen Yang 005 (ICTA, 2023)

POSS-CNN: An Automatically Generated Convolutional Neural Network with Precision and Operation Separable Structure Aiming at Target Recognition and Detection. - Jia Hou; Jingyu Zhang; Qi Chen; Siwei Xiang; Yishuo Meng; Jianfei Wang 003; Cimang Lu; Chen Yang 005 (Inf., 2023)

DRGN: a dynamically reconfigurable accelerator for graph neural networks. - Chen Yang 005; Kaibo Huo; Long-Fei Geng; Kuizhi Mei (J. Ambient Intell. Humaniz. Comput., 2023)

TCPM: A Reconfigurable and Efficient Toom-Cook-Based Polynomial Multiplier Over Rings Using a Novel Compressed Postprocessing Algorithm. - Jianfei Wang 003; Chen Yang 005; Fahong Zhang 002; Yishuo Meng; Yang Su 003 (IEEE Trans. Very Large Scale Integr. Syst., 2023)

An Efficient CNN Accelerator Achieving High PE Utilization Using a Dense-/Sparse-Aware Redundancy Reduction Method and Data-Index Decoupling Workflow. - Yishuo Meng; Chen Yang 005; Siwei Xiang; Jianfei Wang 003; Kuizhi Mei; Li Geng (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A High-Throughput and Flexible Architecture Based on a Reconfigurable Mixed-Radix FFT With Twiddle Factor Compression and Conflict-Free Access. - Chen Yang 005; Junfeng Wu; Siwei Xiang; Liyan Liang; Li Geng (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A Real-Time and Efficient Optical Flow Tracking Accelerator on FPGA Platform. - Yifan Gong 005; Jinshuo Zhang; Xin Liu; Jialin Li; Ying Lei; Zhe Zhang; Chen Yang 005; Li Geng (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

LSTM-CRP: Algorithm-Hardware Co-Design and Implementation of Cache Replacement Policy Using Long Short-Term Memory. - Yizhou Wang 004; Yishuo Meng; Jiaxing Wang; Chen Yang 005 (Big Data Cogn. Comput., 2024)

An Efficient and Scalable FHE-Based PDQ Scheme: Utilizing FFT to Design a Low Multiplication Depth Large-Integer Comparison Algorithm. - Fahong Zhang 002; Chen Yang 005; Rui Zong; Xinran Zheng; Jianfei Wang 003; Yishuo Meng (IEEE Trans. Inf. Forensics Secur., 2024)

A High-Throughput Toom-Cook-4 Polynomial Multiplier for Lattice-Based Cryptography Using a Novel Winograd-Schoolbook Algorithm. - Jianfei Wang 003; Chen Yang 005; Fahong Zhang 002; Yishuo Meng; Siwei Xiang; Yang Su 003 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

WRA-SS: A High-Performance Accelerator Integrating Winograd With Structured Sparsity for Convolutional Neural Networks. - Chen Yang 005; Yishuo Meng; Jiawei Xi; Siwei Xiang; Jianfei Wang 003; Kuizhi Mei (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Flexible and Efficient Convolutional Acceleration on Unified Hardware Using the Two-Stage Splitting Method and Layer-Adaptive Allocation of 1-D/2-D Winograd Units. - Chen Yang 005; Yaoyao Yang; Yishuo Meng; Kaibo Huo; Siwei Xiang; Jianfei Wang 003; Li Geng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

A High-Throughput and Scalable Schoolbook Polynomial Multiplier for Accelerating Saber on FPGA Using a Novel Winograd-Based Architecture. - Jianfei Wang 003; Chen Yang 005; Fahong Zhang 002; Jia Hou; Yishuo Meng; Siwei Xiang; Yang Su 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

ALSCA: A Large-Scale Sparse CNN Accelerator Using Position-First Dataflow and Input Channel Merging Approach. - Yishuo Meng; Siwei Xiang; Jianfei Wang 003; Jia Hou; Chen Yang 005 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A Novel Two-Level Protection Scheme against Hardware Trojans on a Reconfigurable CNN Accelerator. - Zichu Liu; Jia Hou; Jianfei Wang 003; Chen Yang 005 (Cryptogr., 2024)

A Real-Time and High Precision Hardware Implementation of RANSAC Algorithm for Visual SLAM Achieving Mismatched Feature Point Pair Elimination. - Wenzheng He; Zikuo Lu; Xin Liu; Ziwei Xu; Jingshuo Zhang; Chen Yang 005; Li Geng (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A Lightweight and Efficient Encryption/Decryption Coprocessor for RLWE-Based Cryptography. - Yushu Yang; Zihang Wang; Jianfei Wang 003; Jia Hou; Yang Su 003; Chen Yang 005 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Low Multiplicative Depth Polynomial Evaluation Architectures for Homomorphic Encrypted Data. - Jianfei Wang 003; Jia Hou; Fahong Zhang 002; Yishuo Meng; Yang Su 003; Chen Yang 005 (ASP-DAC, 2025)

An Efficient and Parallelism-Scalable Large Integer Multiplier Architecture Using Least-Positive Form and Winograd Fast Algorithm. - Jianfei Wang 003; Jia Hou; Fahong Zhang 002; Yishuo Meng; Yang Su 003; Chen Yang 005 (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

A Compact and Efficient Hardware Accelerator for RNS-CKKS En/Decoding and En/Decryption. - Jianfei Wang 003; Chen Yang 005; Jia Hou; Fahong Zhang 002; Yishuo Meng; Yang Su 003; Leibo Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

A High-Throughput and Flexible CNN Accelerator Based on Mixed-Radix FFT Method. - Yishuo Meng; Junfeng Wu; Siwei Xiang; Jianfei Wang 003; Jia Hou; Zhijie Lin; Chen Yang 005 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A Scalable and Efficient NTT/INTT Architecture Using Group-Based Pairwise Memory Access and Fast Interstage Reordering. - Zihang Wang; Yushu Yang; Jianfei Wang 003; Jia Hou; Yang Su 003; Chen Yang 005 (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A Reconfigurable and Area-Efficient Polynomial Multiplier Using a Novel In-Place Constant-Geometry NTT/INTT and Conflict-Free Memory Mapping Scheme. - Jianfei Wang 003; Chen Yang 005; Yishuo Meng; Fahong Zhang 002; Jia Hou; Siwei Xiang; Yang Su 003 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A Scalable and Efficient Architecture for Binary Polynomial Multiplication in BIKE Utilizing Inter-/Inner-Wise Sparsity and Block-by-Block Pipeline. - Jia Hou; Jianfei Wang 003; Yishuo Meng; Fahong Zhang 002; Yang Su 003; Chen Yang 005 (IEEE Trans. Very Large Scale Integr. Syst., 2025)

Rethinking the Designing of Convolution Engine for Reconfigurable CNN Accelerator Using Sparse-Based Design Scheme. - Yishuo Meng; Jianfei Wang 003; Siwei Xiang; Jia Hou; Zhijie Lin; Kuizhi Mei; Chen Yang 005 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A High-Performance SCNN Accelerator Using Parallel Sparsity Detection and Index-Oriented Computation Workflow. - Yishuo Meng; Jianfei Wang 003; Qiang Fu; Jia Hou; Siwei Xiang; Ge Li; Chen Yang 005 (IEEE Trans. Very Large Scale Integr. Syst., 2025)