Efficient VLSI Architectures for a High-Performance Digital Image Communication System. - Chen-Yi Lee; Francky Catthoor; Hugo De Man (IEEE J. Sel. Areas Commun., 1990)

Breaking the bottleneck of sequential decoding for high-speed digital communication. - Chen-Yi Lee; Francky Catthoor; Hugo De Man (ICASSP, 1991)

An area-efficient maximum/minimum detection circuit for digital and video signal processing. - Chen-Yi Lee; Shih-Chou Juan; Wen-Wei Yang (ISCAS, 1993)

VLSI implementation of an M-array image filter based on shift register array. - Chen-Yi Lee; Jer-Min Tsai; Shih-Chieh Hsu (Integr., 1993)

Finite State Vector Quantization with Multi-Path Tree Search Strategy for Image/Video Coding. - Shih-Chou Juan; Yen-Jean Chao; Chen-Yi Lee (ISCAS, 1994)

Design of a Fast Sequential Decoding Algorithm Based on Dynamic Searching Strategy. - Wen-Wei Yang; Li-Fu Jeng; Chen-Yi Lee (ISCAS, 1994)

High-Throughput Data Compressor Designs Using Content Addressable Memory. - Ren-Yang Yang; Chen-Yi Lee (ISCAS, 1994)

High-speed median filter designs using shiftable content-addressable memory. - Chen-Yi Lee; Po-Wen Hsieh; Jer-Min Tsai (IEEE Trans. Circuits Syst. Video Technol., 1994)

Semi-systolic array based motion estimation processor design. - Mei-Cheng Lu; Chen-Yi Lee (ICASSP, 1995)

A New Multi-Path Tree-Search FSVQ Architecture for Image/Video Sequence Coding. - Yen-Juan Chao; Chen-Yi Lee (ISCAS, 1995)

An Efficient Memory Architecture for Motion Estimation Processor Design. - Eddie G. Tzeng; Chen-Yi Lee (ISCAS, 1995)

A shift register architecture for high-speed data sorting. - Chen-Yi Lee; Jer-Min Tsai (J. VLSI Signal Process., 1995)

Scalable VLSI architectures for full-search block matching algorithms. - Yuan-Hau Yeh; Chen-Yi Lee (ICIP (2), 1996)

The outage probability in DS/CDMA for cellular mobile radio with imperfect power control. - Terng-Yin Hsu; Chen-Yi Lee (PIMRC, 1996)

Finite state vector quantization with multipath tree search strategy for image/video coding. - Chen-Yi Lee; Shih-Chou Juan; Yen-Juan Chao (IEEE Trans. Circuits Syst. Video Technol., 1996)

Buffer size optimization for full-search block matching algorithms. - Yuan-Hau Yeh; Chen-Yi Lee (ASAP, 1997)

A multicasting solution for ATM video applications. - Jer-Min Tsai; Hsin-Hsiung Fang; Chen-Yi Lee (IEEE Trans. Circuits Syst. Video Technol., 1997)

An Efficient VLSI Architecture for Full-Search Block Matching Algorithms. - Chen-Yi Lee; Mei-Cheng Lu (J. VLSI Signal Process., 1997)

Entropy-constrained gradient-match vector quantization for image coding. - Shin-Chou Juan; Chen-Yi Lee (ICASSP, 1998)

An efficient VLC decompression scheme for user-defined coding tables. - Bai-Jue Shieh; Chen-Yi Lee (ICASSP, 1999)

A Cost-Effective Lighting Processor for 3D Graphics Application. - Cheng-Hsien Chen; Chen-Yi Lee (ICIP (2), 1999)

An Efficient VLSI Architecture for Separable 2-D Discrete Wavelet Transform. - Wen-Shiaw Peng; Chen-Yi Lee (ICIP (2), 1999)

A New Anti-Aliasing Algorithm for Computer Graphics Images. - Yuan-Hau Yeh; Chen-Yi Lee (ICIP (2), 1999)

An all-digital phase-locked loop (ADPLL)-based clock recovery circuit. - Terng-Yin Hsu; Bai-Jue Shieh; Chen-Yi Lee (IEEE J. Solid State Circuits, 1999)

Cost-effective VLSI architectures and buffer size optimization for full-search block matching algorithms. - Yuan-Hau Yeh; Chen-Yi Lee (IEEE Trans. Very Large Scale Integr. Syst., 1999)

FORTE-VLC: A forward tracing self-error correction variable length code for image coding in wireless application. - Yew-San Lee; Keng-Khai Ong; Wei-Shin Chang; Chen-Yi Lee (EUSIPCO, 2000)

HVLC: error correctable hybrid variable length code for image coding in wireless transmission. - Yew-San Lee; Cheng-Mou Yu; Wei-Shin Chang; Chen-Yi Lee (ICASSP, 2000)

Construction of Error Resilient Synchronization Codeword for Variable-Length Code in Image Transmission. - Yew-San Lee; Wei-Shin Chang; Hsin-Han Ho; Chen-Yi Lee (ICIP, 2000)

A new approach of group-based VLC codec system. - Bai-Jue Shieh; Terng-Yin Hsu; Chen-Yi Lee (ISCAS, 2000)

A high-throughput memory-based VLC decoder with codeword boundary prediction. - Bai-Jue Shieh; Yew-San Lee; Chen-Yi Lee (IEEE Trans. Circuits Syst. Video Technol., 2000)

An area-efficient architecture for Reed-Solomon decoder using the inversionless decomposed Euclidean algorithm. - Hsie-Chia Chang; Chen-Yi Lee (ISCAS (2), 2001)

A line-based, memory efficient and programmable architecture for 2D DWT using lifting scheme. - Wei-Hsin Chang; Yew-San Lee; Wen-Shiaw Peng; Chen-Yi Lee (ISCAS (4), 2001)

A novel subcircuit extraction algorithm by recursive identification scheme. - Wei-Hsin Chang; Shuenn-Der Tzeng; Chen-Yi Lee (ISCAS (5), 2001)

A novel structure for portable digitally controlled oscillator. - Jin-Jer Jong; Chen-Yi Lee (ISCAS (1), 2001)

Error resilient hybrid variable length codec with tough error synchronization for wireless image transmission. - Yew-San Lee; Cheng-Mou Yu; Chen-Yi Lee (ISCAS (4), 2001)

A wideband digital frequency synthesizer. - Yi-Chuan Liu; Chung-Cheng Wang; Terng-Yin Hsu; Chen-Yi Lee (ISCAS (4), 2001)

A novel single-bit input all digital synchronizer and demodulator baseband processor for fast frequency hopping system. - Frank S. Tsai; Chen-Yi Lee (ISCAS (4), 2001)

A Reed-Solomon product-code (RS-PC) decoder chip for DVD applications. - Hsie-Chia Chang; C. Bernard Shung; Chen-Yi Lee (IEEE J. Solid State Circuits, 2001)

A new approach of group-based VLC codec system with full table programmability. - Bai-Jue Shieh; Yew-San Lee; Chen-Yi Lee (IEEE Trans. Circuits Syst. Video Technol., 2001)

FPGA education and research activities in Taiwan. - Yu-Tsang Chang; Yu-Te Chou; Wei-Chang Tsai; Jiann-Jenn Wang; Chen-Yi Lee (FPT, 2002)

A novel DCT-based bit plane error resilient entropy coding for wireless multimedia communication. - Yew-San Lee; Cheng-Mou Yu; Chen-Yi Lee (ICASSP, 2002)

Error resilient image coding and smart post-processing error concealment for wireless image transmission. - Keng-Khai Ong; Yew-San Lee; Chen-Yi Lee (ICASSP, 2002)

A high throughput low cost context-based adaptive arithmetic codec for multiple standards. - Keng-Khai Ong; Wei-Hsin Chang; Yi-Chen Tseng; Yew-San Lee; Chen-Yi Lee (ICIP (1), 2002)

A novel fixed bit plane error resilient image coding for wireless multimedia transmission. - Hung-Kuo Wei; Yew-San Lee; Yen-Hsu Shih; Chen-Yi Lee (ICIP (3), 2002)

A novel DCT-based bit plane error resilient entropy coding scheme and codec for wireless image communication. - Yew-San Lee; Cheng-Mou Yu; Hung-Kuo Wei; Yen-Hsu Shih; Chen-Yi Lee (ISCAS (5), 2002)

A high throughput context-based adaptive arithmetic codec for JPEG2000. - Keng-Khai Ong; Wei-Hsin Chang; Yi-Chen Tseng; Yew-San Lee; Chen-Yi Lee (ISCAS (4), 2002)

Reduce the Memory Bandwidth of 3D Graphics Hardware with a Novel Rasterizer. - Cheng-Hsien Chen; Chen-Yi Lee (J. Circuits Syst. Comput., 2002)

Design of a wide-band frequency synthesizer based on TDC and DVC techniques. - Terng-Yin Hsu; Terng-Ren Hsu; Chung-Cheng Wang; Yi-Chuan Liu; Chen-Yi Lee (IEEE J. Solid State Circuits, 2002)

A JPEG-like texture compression with adaptive quantization for 3D graphics application. - Cheng-Hsien Chen; Chen-Yi Lee (Vis. Comput., 2002)

A low power and high speed Viterbi decoder chip for WLAN applications. - Chien-Ching Lin; Chia-Cho Wu; Chen-Yi Lee (ESSCIRC, 2003)

Combining adaptive smoothing and decision-directed channel estimation schemes for OFDM WLAN systems. - Hsuan-Yu Liu; Yi-Hsin Yu; Chien-Jen Hung; Temg-Yin Hsu; Chen-Yi Lee (ISCAS (2), 2003)

A Design of CMOS Broadband Amplifier With High-Q Active Inductor. - Jhy-Neng Yang; Yi-Chang Cheng; Chen-Yi Lee (IWSOC, 2003)

Infrastructure for Education and Research of SOC/IP in Taiwan. - Wei-Chang Tsai; Chun-Ming Huang; Jiann-Jenn Wang; Chen-Yi Lee (MSE, 2003)

A Low-Power Design for Reed-Solomon Decoders. - Hsie-Chia Chang; Chen-Yi Lee (J. Circuits Syst. Comput., 2003)

An all-digital phase-locked loop for high-speed clock generation. - Ching-Che Chung; Chen-Yi Lee (IEEE J. Solid State Circuits, 2003)

Error-resilient image coding (ERIC) with smart-IDCT error concealment technique for wireless multimedia transmission. - Yew-San Lee; Keng-Khai Ong; Chen-Yi Lee (IEEE Trans. Circuits Syst. Video Technol., 2003)

Two-level hierarchical Z-buffer with compression technique for 3D graphics hardware. - Cheng-Hsien Chen; Chen-Yi Lee (Vis. Comput., 2003)

A dual mode channel decoder for 3GPP2 mobile wireless communications. - Chien-Ching Lin; Yen-Hsu Shih; Hsie-Chia Chang; Chen-Yi Lee (ESSCIRC, 2004)

A low-complexity soft vlc decoder using performance modeling. - Tsu-Ming Liu; Chen-Yi Lee (ICIP, 2004)

A low-power group-based VLD design. - Cheng-Hung Liu; Bai-Jue Shieh; Chen-Yi Lee (ISCAS (2), 2004)

A power and area efficient multi-mode FEC processor. - Yi-Chen Tseng; Chien-Ching Lin; Hsie-Chia Chang; Chen-Yi Lee (ISCAS (2), 2004)

Enhanced Stochastic Bit Reshuffling for Fine Granular Scalable Video Coding. - Wen-Hsiao Peng; Tihao Chiang; Hsueh-Ming Hang; Chen-Yi Lee (PCM (2), 2004)

A new DLL-based approach for all-digital multiphase clock generation. - Ching-Che Chung; Chen-Yi Lee (IEEE J. Solid State Circuits, 2004)

A dynamic scaling FFT processor for DVB-T applications. - Yu-Wei Lin; Hsuan-Yu Liu; Chen-Yi Lee (IEEE J. Solid State Circuits, 2004)

A 3.33Gb/s (1200,720) low-density parity check code decoder. - Chien-Ching Lin; Kai-Li Lin; Hsie-Chia Chang; Chen-Yi Lee (ESSCIRC, 2005)

An area-efficient and high-throughput de-blocking filter for multi-standard video applications. - Tsu-Ming Liu; Wen-Ping Lee; Chen-Yi Lee (ICIP (3), 2005)

An all-digital PLL with cascaded dynamic phase average loop for wide multiplication range applications. - Pao-Lung Chen; Ching-Che Chung; Chen-Yi Lee (ISCAS (5), 2005)

Predictive equalizer design for DVB-T system. - Ting-An Lin; Chen-Yi Lee (ISCAS (2), 2005)

An H.264/AVC decoder with 4×4-block level pipeline. - Ting-An Lin; Sheng-Zen Wang; Tsu-Ming Liu; Chen-Yi Lee (ISCAS (2), 2005)

A memory-efficient deblocking filter for H.264/AVC video coding. - Tsu-Ming Liu; Wen-Ping Lee; Ting-An Lin; Chen-Yi Lee (ISCAS (3), 2005)

A new motion compensation design for H.264/AVC decoder. - Sheng-Zen Wang; Ting-An Lin; Tsu-Ming Liu; Chen-Yi Lee (ISCAS (5), 2005)

A novel technique for I/Q imbalance and CFO compensation in OFDM systems. - Jui-Yuan Yu; Ming-Fu Sun; Terng-Yin Hsu; Chen-Yi Lee (ISCAS (6), 2005)

A Standard Cell-Based Frequency Synthesizer with Dynamic Frequency Counting. - Pao-Lung Chen; Chen-Yi Lee (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

A 1-GS/s FFT/IFFT processor for UWB applications. - Yu-Wei Lin; Hsuan-Yu Liu; Chen-Yi Lee (IEEE J. Solid State Circuits, 2005)

A portable digitally controlled oscillator using novel varactors. - Pao-Lung Chen; Ching-Che Chung; Chen-Yi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2005)

Design of a power-reduction Viterbi decoder for WLAN applications. - Chien-Ching Lin; Yen-Hsu Shih; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

Guest Editorial: System-on-a-Chip for Multimedia Systems. - Yen-Kuang Chen; Stella Kuei-Ann Wen; Chen-Yi Lee (J. VLSI Signal Process., 2005)

An Improved Soft-Input CAVLC Decoder for Mobile Communication Applications. - Tsu-Ming Liu; Chen-Yi Lee (APCCAS, 2006)

A Fast-Lock-In ADPLL with High-Resolution and Low-Power DCO for SoC Applications. - Duo Sheng; Ching-Che Chung; Chen-Yi Lee (APCCAS, 2006)

A Self-Grouping and Table-Merging Algorithm for VLC-Based Video Decoding System. - Shao-Ming Sun; Tsu-Ming Liu; Chen-Yi Lee (APCCAS, 2006)

Design of a 125muW, fully-scalable MPEG-2 and H.264/AVC video decoder for mobile applications. - Tsu-Ming Liu; Ching-Che Chung; Chen-Yi Lee; Ting-An Lin; Sheng-Zen Wang (DAC, 2006)

A 1.8V 250mW COFDM baseband receiver for DVB-T/H applications. - Lei-Fone Chen; Yuan Chen; Lu-Chung Chien; Ying-Hao Ma; Chia-Hao Lee; Yu-Wei Lin; Chien-Ching Lin; Hsuan-Yu Liu; Terng-Yin Hsu; Chen-Yi Lee (ISSCC, 2006)

A 125µw, fully scalable MPEG-2 and H.264/AVC video decoder for mobile applications. - Tsu-Ming Liu; Ting-An Lin; Sheng-Zen Wang; Wen-Ping Lee; Kang-Cheng Hou; Jiun-Yan Yang; Chen-Yi Lee (ISSCC, 2006)

A low-power dual-mode video decoder for mobile applications. - Tsu-Ming Liu; Ting-An Lin; Sheng-Zen Wang; Chen-Yi Lee (IEEE Commun. Mag., 2006)

A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications. - Pao-Lung Chen; Ching-Che Chung; Jyh-Neng Yang; Chen-Yi Lee (IEEE J. Solid State Circuits, 2006)

A Low-Complexity Synchronizer for OFDM-Based UWB System. - Hsuan-Yu Liu; Chen-Yi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

A Context Adaptive Bit-Plane Coder With Maximum-Likelihood-Based Stochastic Bit-Reshuffling Technique for Scalable Video Coding. - Wen-Hsiao Peng; Tihao Chiang; Hsueh-Ming Hang; Chen-Yi Lee (IEEE Trans. Multim., 2006)

A low power turbo/Viterbi decoder for 3GPP2 applications. - Chien-Ching Lin; Yen-Hsu Shih; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Very Large Scale Integr. Syst., 2006)

A 0.22 nJ/b/iter 0.13 μm turbo decoder chip using inter-block permutation interleaver. - Cheng-Chi Wong; Cheng-Hao Tang; Ming-Wei Lai; Yan-Xiu Zheng; Chien-Ching Lin; Hsie-Chia Chang; Chen-Yi Lee; Yu.-T. Su (CICC, 2007)

A sub-mW Multi-Tone CDMA Baseband Transceiver Chipset for Wireless Body Area Network Applications. - Jui-Yuan Yu; Ching-Che Chung; Wan-Chun Liao; Chen-Yi Lee (ISSCC, 2007)

An all-digital phase-frequency tunable clock generator for wireless OFDM communications systems. - Jui-Yuan Yu; Juinn-Ting Chen; Mei-Hui Yang; Ching-Che Chung; Chen-Yi Lee (SoCC, 2007)

Design of a DVB-T/H COFDM Receiver for Portable Video Applications [Topics in Circuits for Communications]. - Lei-Fone Chen; Chen-Yi Lee (IEEE Commun. Mag., 2007)

MLP/BP-Based Soft Decision Feedback Equalization with Bit-Interleaved TCM for Wireless Applications. - Terng-Ren Hsu; Chien-Ching Lin; Terng-Yin Hsu; Chen-Yi Lee (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

A 125 µW, Fully Scalable MPEG-2 and H.264/AVC Video Decoder for Mobile Applications. - Tsu-Ming Liu; Ting-An Lin; Sheng-Zen Wang; Wen-Ping Lee; Jiun-Yan Yang; Kang-Cheng Hou; Chen-Yi Lee (IEEE J. Solid State Circuits, 2007)

Design of an FFT/IFFT Processor for MIMO OFDM Systems. - Yu-Wei Lin; Chen-Yi Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications. - Duo Sheng; Ching-Che Chung; Chen-Yi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

An In/Post-Loop Deblocking Filter With Hybrid Filtering Schedule. - Tsu-Ming Liu; Wen-Ping Lee; Chen-Yi Lee (IEEE Trans. Circuits Syst. Video Technol., 2007)

A New Soft Variable Length Decoder for Wireless Video Transmission. - Tsu-Ming Liu; Sheng-Zen Wang; Bai-Jue Shieh; Chen-Yi Lee (IEEE Trans. Circuits Syst. Video Technol., 2007)

Design of a memory-based VLC decoder for portable video applications. - Wei-Chin Lee; Yao Li; Chen-Yi Lee (APCCAS, 2008)

An all digital spread spectrum clock generator with programmable spread ratio for SoC applications. - Duo Sheng; Ching-Che Chung; Chen-Yi Lee (APCCAS, 2008)

Multi-mode message passing switch networks applied for QC-LDPC decoder. - Chih-Hao Liu; Chien-Ching Lin; Hsie-Chia Chang; Chen-Yi Lee; Yarsun Hsua (ISCAS, 2008)

A 2.4-Gsample/s DVFS FFT Processor for MIMO OFDM Communication Systems. - Yuan Chen; Yu-Wei Lin; Yu-Chi Tsao; Chen-Yi Lee (IEEE J. Solid State Circuits, 2008)

An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications. - Chih-Hao Liu; Shau-Wei Yen; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee; Yar-Sun Hsu; Shyh-Jye Jou (IEEE J. Solid State Circuits, 2008)

An Indexed-Scaling Pipelined FFT Processor for OFDM-Based WPAN Applications. - Yuan Chen; Yu-Chi Tsao; Yu-Wei Lin; Chin-Hung Lin; Chen-Yi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems. - Jui-Yuan Yu; Ching-Che Chung; Chen-Yi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

Design of an H.264/AVC Decoder with Memory Hierarchy and Line-Pixel-Lookahead. - Tsu-Ming Liu; Chen-Yi Lee (J. Signal Process. Syst., 2008)

A 0.92mm2 23.4mW fully-compliant CTC decoder for WiMAX 802.16e application. - Shao-Wei Yen; Ming-Chih Hu; Chin-Lung Chen; Hsie-Chia Chang; Shyh-Jye Jou; Chen-Yi Lee (CICC, 2009)

A 11.5-Gbps LDPC decoder based on CP-PEG code construction. - Chih-Lung Chen; Kao-Shou Lin; Hsie-Chia Chang; Wai-Chi Fang; Chen-Yi Lee (ESSCIRC, 2009)

A 1.69 Gb/s area-efficient AES crypto core with compact on-the-fly key expansion unit. - Po-Chun Liu; Hsie-Chia Chang; Chen-Yi Lee (ESSCIRC, 2009)

Design of an Intra Predictor with Data Reuse for High-profile H.264 Applications. - Yu-Fan Lai; Tsu-Ming Liu; Yao Li; Chen-Yi Lee (ISCAS, 2009)

An eCrystal Oscillator with Self-calibration Capability. - Chien-Ying Yu; Jui-Yuan Yu; Chen-Yi Lee (ISCAS, 2009)

A 0.5 V 4.85 Mbps Dual-Mode Baseband Transceiver With Extended Frequency Calibration for Biotelemetry Applications. - Tsan-Wen Chen; Jui-Yuan Yu; Chien-Ying Yu; Chen-Yi Lee (IEEE J. Solid State Circuits, 2009)

A Universal VLSI Architecture for Reed-Solomon Error-and-Erasure Decoders. - Hsie-Chia Chang; Chien-Ching Lin; Fu-Ke Chang; Chen-Yi Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network. - Chih-Hao Liu; Chien-Ching Lin; Shao-Wei Yen; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee; Yar-Sun Hsu; Shyh-Jye Jou (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

A low-power radix-4 Viterbi decoder based on DCVSPG pulsed latch with sharing technique. - Xin-Ru Lee; Hsie-Chia Chang; Chen-Yi Lee (APCCAS, 2010)

A 521-bit dual-field elliptic curve cryptographic processor with power analysis resistance. - Jen-Wei Lee; Yao-Lin Chen; Chih-Yeh Tseng; Hsie-Chia Chang; Chen-Yi Lee (ESSCIRC, 2010)

An improved soft BCH decoder with one extra error compensation. - Yi-Min Lin; Hsie-Chia Chang; Chen-Yi Lee (ISCAS, 2010)

Tunable magnetic alginate microspheres by using a microfluidic device. - Chen-Yi Lee; Song-Bin Huang; Kang-Yi Lien; Ming-Yang Lin; Gwo-Bin Lee (NEMS, 2010)

Fast-lock all-digital DLL and digitally-controlled phase shifter for DDR controller applications. - Duo Sheng; Ching-Che Chung; Chen-Yi Lee (IEICE Electron. Express, 2010)

A Low Power Differential Cascode Voltage Switch with Pass Gate Pulsed Latch for Viterbi Decoder. - Po-Tsang Huang; Xin-Ru Lee; Hsie-Chia Chang; Chen-Yi Lee; Wei Hwang (J. Low Power Electron., 2010)

A 26.9 K 314.5 Mb/s Soft (32400, 32208) BCH Decoder Chip for DVB-S2 System. - Yi-Min Lin; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee (IEEE J. Solid State Circuits, 2010)

Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture. - Cheng-Chi Wong; Ming-Wei Lai; Chien-Ching Lin; Hsie-Chia Chang; Chen-Yi Lee (IEEE J. Solid State Circuits, 2010)

A Generalized Mixed-Radix Algorithm for Memory-Based FFT Processors. - Chen-Fong Hsiao; Yuan Chen; Chen-Yi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

A Sub-10-muhboxW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications. - Shu-Yu Hsu; Jui-Yuan Yu; Chen-Yi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

A Low Overhead DPA Countermeasure Circuit Based on Ring Oscillators. - Po-Chun Liu; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

A 0.67mW 14.55Mbps OFDM-based sensor node transmitter for body channel communications. - Tsan-Wen Chen; Ping-Yuan Tsai; Jui-Yuan Yu; Chen-Yi Lee (A-SSCC, 2011)

A micropower biomedical signal processor for mobile healthcare applications. - Shu-Yu Hsu; Yao-Lin Chen; Po-Yao Chang; Jui-Yuan Yu; Ten-Fang Yang; Ray-Jade Chen; Chen-Yi Lee (A-SSCC, 2011)

A low power all-digital signal component separator for uneven multi-level LINC systems. - Tsan-Wen Chen; Ping-Yuan Tsai; Dieter De Moitie; Jui-Yuan Yu; Chen-Yi Lee (ESSCIRC, 2011)

A 2.97 Gb/s DPA-resistant AES engine with self-generated random sequence. - Po-Chun Liu; Ju-Hung Hsiao; Hsie-Chia Chang; Chen-Yi Lee (ESSCIRC, 2011)

A dual-field elliptic curve cryptographic processor with a radix-4 unified division unit. - Yao-Lin Chen; Jen-Wei Lee; Po-Chun Liu; Hsie-Chia Chang; Chen-Yi Lee (ISCAS, 2011)

An area-efficient high-accuracy prediction-based CABAC decoder architecture for H.264/AVC. - Ming-Yu Kuo; Yao Li; Chen-Yi Lee (ISCAS, 2011)

Hardware-Assisted Reliability Enhancement for Embedded Multi-core Virtualization Design. - Tsung-Han Lin; Yuki Kinebuchi; Alexandre Courbot; Hiromasa Shimada; Takushi Morita; Hitoshi Mitake; Chen-Yi Lee; Tatsuo Nakajima (ISORC, 2011)

Hardware-Assisted Reliability Enhancement for Embedded Multi-core Virtualization Design. - Tsung-Han Lin; Yuki Kinebuchi; Hiromasa Shimada; Hitoshi Mitake; Chen-Yi Lee; Tatsuo Nakajima (RTCSA (2), 2011)

An energy-efficient OFDM-based baseband transceiver design for ubiquitous healthcare monitoring applications. - Tzu-Chun Shih; Tsan-Wen Chen; Wei-Hao Sung; Ping-Yuan Tsai; Chen-Yi Lee (SoCC, 2011)

A low-power all-digital phase modulator pair for LINC transmitters. - Ping-Yuan Tsai; Tsan-Wen Chen; Chen-Yi Lee (SoCC, 2011)

A Sub-mW All-Digital Signal Component Separator With Branch Mismatch Compensation for OFDM LINC Transmitters. - Tsan-Wen Chen; Ping-Yuan Tsai; Jui-Yuan Yu; Chen-Yi Lee (IEEE J. Solid State Circuits, 2011)

A Predefined Bit-Plane Comparison Coding for Mobile Video Applications. - Chien-Chen Lin; Yao Li; Chen-Yi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A MPCN-Based Parallel Architecture in BCH Decoders for nand Flash Memory Devices. - Yi-Min Lin; Chi-Heng Yang; Chih-Hsiang Hsu; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A Robust Frequency Tracking Loop for Energy-Efficient Crystalless WBAN Systems. - Wei-Hao Sung; Jui-Yuan Yu; Chen-Yi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A Low-Power and Portable Spread Spectrum Clock Generator for SoC Applications. - Duo Sheng; Ching-Che Chung; Chen-Yi Lee (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A 90 nm All-digital Smart Temperature Sensor with Wireless Body Area Network Baseband Transceiver for Biotelemetry Applications. - Ching-Che Chung; Jui-Yuan Yu; Shiou-Ru Jang; Chen-Yi Lee (J. Signal Process. Syst., 2011)

A memory-efficient architecture for intra predictor and de-blocking filter in video coding system. - Chia-Lin Liu; Chang-Hung Tsai; Hsiuan-Ting Wang; Yao Li; Chen-Yi Lee (APCCAS, 2012)

A 4.88µW ECG delineator using wavelet transform for mobile healthcare application. - Po-Yao Chang; Shu-Yu Hsu; Chen-Yi Lee (BioCAS, 2012)

An Efficient Countermeasure against Correlation Power-Analysis Attacks with Randomized Montgomery Operations for DF-ECC Processor. - Jen-Wei Lee; Szu-Chi Chung; Hsie-Chia Chang; Chen-Yi Lee (CHES, 2012)

A high-performance elliptic curve cryptographic processor over GF(p) with SPA resistance. - Szu-Chi Chung; Jen-Wei Lee; Hsie-Chia Chang; Chen-Yi Lee (ISCAS, 2012)

Stochastic decoding for LDPC convolutional codes. - Xin-Ru Lee; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee (ISCAS, 2012)

Extrinsic data compression method for double-binary turbo codes. - Yi-Huan Ou-Yang; Chien-Yu Kao; Jen-Yuan Hsu; Pangan Ting; Chen-Yi Lee (ISCAS, 2012)

Spatial Isolation on Realtime Hypervisor using Core-local Memory. - Daisuke Yamaguchi; Takumi Yajima; Chen-Yi Lee; Hiromasa Shimada; Yuki Kinebuchi; Tatsuo Nakajima (PECCS, 2012)

A low cost DPA-resistant 8-bit AES core based on ring oscillators. - Hsing-Ping Fu; Ju-Hung Hsiao; Po-Chun Liu; Hsie-Chia Chang; Chen-Yi Lee (VLSI-DAT, 2012)

A sub-100µW multi-functional cardiac signal processor for mobile healthcare applications. - Shu-Yu Hsu; Yingchieh Ho; Yuhwai Tseng; Ting-You Lin; Po-Yao Chang; Jen-Wei Lee; Ju-Hung Hsiao; Siou-Ming Chuang; Tze-Zheng Yang; Po-Chun Liu; Ten-Fang Yang; Ray-Jade Chen; et al. (VLSIC, 2012)

A 2.37-Gb/s 284.8 mW Rate-Compatible (491, 3, 6) LDPC-CC Decoder. - Chih-Lung Chen; Yu-Hsiang Lin; Hsie-Chia Chang; Chen-Yi Lee (IEEE J. Solid State Circuits, 2012)

A 5.79-Gb/s Energy-Efficient Multirate LDPC Codec Chip for IEEE 802.15.3c Applications. - Shao-Wei Yen; Shiang-Yu Hung; Chih-Lung Chen; Hsie-Chia Chang; Shyh-Jye Jou; Chen-Yi Lee (IEEE J. Solid State Circuits, 2012)

An Efficient DPA Countermeasure With Randomized Montgomery Operations for DF-ECC Processor. - Jen-Wei Lee; Ju-Hung Hsiao; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A True Random-Based Differential Power Analysis Countermeasure Circuit for an AES Engine. - Po-Chun Liu; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A Low-Power DCO Using Interlaced Hysteresis Delay Cells. - Chien-Ying Yu; Ching-Che Chung; Chia-Jung Yu; Chen-Yi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A Low Voltage All-Digital On-Chip Oscillator Using Relative Reference Modeling. - Chien-Ying Yu; Jui-Yuan Yu; Chen-Yi Lee (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Processor with side-channel attack resistance. - Jen-Wei Lee; Szu-Chi Chung; Hsie-Chia Chang; Chen-Yi Lee (ISSCC, 2013)

A digital microfluidic processor for biomedical applications. - Kelvin Yi-Tse Lai; Yu-Tao Yang; Gary Wang; Yi-Wen Lu; Chen-Yi Lee (SiPS, 2013)

Strengthening Modern Electronics Industry Through the National Program for Intelligent Electronics in Taiwan. - Wen-Tsuen Chen; Youn-Long Lin; Chen-Yi Lee; Jeng-Long Chiang; Meng-Fan Chang; Shih-Chieh Chang (IEEE Access, 2013)

Improved High Code-Rate Soft BCH Decoder Architectures With One Extra Error Compensation. - Yi-Min Lin; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Very Large Scale Integr. Syst., 2013)

A 1-100Mb/s 0.5-9.9mW LDPC convolutional code decoder for body area network. - Chih-Lung Chen; Sheng-Jhan Wu; Hsie-Chia Chang; Chen-Yi Lee (A-SSCC, 2014)

What is a good way to expand a silicon value to a solution value? - Tzi-Dar Chiueh; Toru Shimizu; Gregory Chen; Chen-Yi Lee; Charles Hsu; Tihao Chiang; Zhihua Wang 001; Junghwan Choi; Jongwoo Lee; Yasumoto Tomita; Takayuki Kawahara (A-SSCC, 2014)

A 3.3V 15.6b 6.1pJ/0.02%RH with 10ms response humidity sensor for respiratory monitoring. - Kelvin Yi-Tse Lai; Yu-Tao Yang; Bang-Jing Chen; Chun-Jen Shen; Ming-Feng Shiu; Zih-Cheng He; Hsie-Chia Chang; Chen-Yi Lee (A-SSCC, 2014)

A 2 GOPS quad-mean shift processor with early termination for machine learning applications. - Chang-Hung Tsai; Hui-Hsuan Lee; Wan-Ju Yu; Chen-Yi Lee (ISCAS, 2014)

Area-efficient TFM-based stochastic decoder design for non-binary LDPC codes. - Chih-Wen Yang; Xin-Ru Lee; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee (ISCAS, 2014)

Event-driven read-out circuits for energy-efficient sensor-SoC's. - Chen-Yi Lee; Kelvin Yi-Tse Lai; Shu-Yu Hsu (VLSI-DAT, 2014)

A 7.11mJ/Gb/query data-driven machine learning processor (D2MLP) for big data analysis and applications. - Chang-Hung Tsai; Tung-Yu Wu; Shu-Yu Hsu; Chia-Ching Chu; Fang-Ju Ku; Ying-Siou Laio; Chih-Lung Chen; Wing Hung Wong; Hsie-Chia Chang; Chen-Yi Lee (VLSIC, 2014)

A 48.6-to-105.2 µW Machine Learning Assisted Cardiac Sensor SoC for Mobile Healthcare Applications. - Shu-Yu Hsu; Yingchieh Ho; Po-Yao Chang; Chauchin Su; Chen-Yi Lee (IEEE J. Solid State Circuits, 2014)

A 2.56 Gb/s Soft RS (255, 239) Decoder Chip for Optical Communication Systems. - Yi-Min Lin; Chih-Hsiang Hsu; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Efficient Power-Analysis-Resistant Dual-Field Elliptic Curve Cryptographic Processor Using Heterogeneous Dual-Processing-Element Architecture. - Jen-Wei Lee; Szu-Chi Chung; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A field-programmable lab-on-a-chip with built-in self-test circuit and low-power sensor-fusion solution in 0.35μm standard CMOS process. - Kelvin Yi-Tse Lai; Ming-Feng Shiu; Yi-Wen Lu; Yingchieh Ho; Yu-Chi Kao; Yu-Tao Yang; Gary Wang; Keng-Ming Liu; Hsie-Chia Chang; Chen-Yi Lee (A-SSCC, 2015)

A 1.31Gb/s, 96.6% utilization stochastic nonbinary LDPC decoder for small cell applications. - Xin-Ru Lee; Chih-Wen Yang; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee (ESSCIRC, 2015)

A 3.46 Gb/s (9141, 8224) LDPC-based ECC scheme and on-line channel estimation for solid-state drive applications. - Kin-Chu Ho; Chih-Lung Chen; Yen-Chin Liao; Hsie-Chia Chang; Chen-Yi Lee (ISCAS, 2015)

An OFDM-based 29.1Mbps 0.22nJ/bit body channel communication baseband transceiver. - Ping-Yuan Tsai; Yu-Yun Chang; Shu-Yu Hsu; Chen-Yi Lee (VLSI-DAT, 2015)

A 7.92 Gb/s 437.2 mW Stochastic LDPC Decoder Chip for IEEE 802.15.3c Applications. - Xin-Ru Lee; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

An Area-Efficient Relaxed Half-Stochastic Decoding Architecture for Nonbinary LDPC Codes. - Xin-Ru Lee; Chih-Wen Yang; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Jointly Designed Nonbinary LDPC Convolutional Codes and Memory-Based Decoder Architecture. - Chia-Lung Lin; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A Hardware-Efficient Sigmoid Function With Adjustable Precision for a Neural Network System. - Chang-Hung Tsai; Yu-Ting Chih; Wing Hung Wong; Chen-Yi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Efficient Hardware Architecture of ηT Pairing Accelerator Over Characteristic Three. - Szu-Chi Chung; Jing-Yu Wu; Hsing-Ping Fu; Jen-Wei Lee; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Very Large Scale Integr. Syst., 2015)

An MPCN-Based BCH Codec Architecture With Arbitrary Error Correcting Capability. - Chi-Heng Yang; Yi-Min Lin; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Very Large Scale Integr. Syst., 2015)

An Intelligent Digital Microfluidic Processor for Biomedical Detection. - Kelvin Yi-Tse Lai; Yu-Tao Yang; Chen-Yi Lee (J. Signal Process. Syst., 2015)

A 7.72 Gb/s LDPC-CC decoder with overlapped architecture for pre-5G wireless communications. - Chia-Lung Lin; Rong-Jie Liu; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee (A-SSCC, 2016)

A 41.3pJ/26.7pJ per neuron weight RBM processor for on-chip learning/inference applications. - Chang-Hung Tsai; Wan-Ju Yu; Wing Hung Wong; Chen-Yi Lee (A-SSCC, 2016)

High-level synthesis for micro-electrode-dot-array digital microfluidic biochips. - Zipeng Li; Kelvin Yi-Tse Lai; Po-Hsien Yu; Tsung-Yi Ho; Krishnendu Chakrabarty; Chen-Yi Lee (DAC, 2016)

Error recovery in a micro-electrode-dot-array digital microfluidic biochip? - Zipeng Li; Kelvin Yi-Tse Lai; Po-Hsien Yu; Krishnendu Chakrabarty; Miroslav Pajic; Tsung-Yi Ho; Chen-Yi Lee (ICCAD, 2016)

Design of a micro-electrode cell for programmable lab-on-CMOS platform. - Yingchieh Ho; Gary Wang; Kelvin Yi-Tse Lai; Yi-Wen Lu; Keng-Ming Liu; Yun-Ming Wang; Chen-Yi Lee (ISCAS, 2016)

Built-in self-test for micro-electrode-dot-array digital microfluidic biochips. - Zipeng Li; Kelvin Yi-Tse Lai; Po-Hsien Yu; Krishnendu Chakrabarty; Tsung-Yi Ho; Chen-Yi Lee (ITC, 2016)

A Variation-Tolerant Subthreshold to Superthreshold Level Shifter for Heterogeneous Interfaces. - Yingchieh Ho; Shu-Yu Hsu; Chen-Yi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

An Efficient Decoder Architecture for Nonbinary LDPC Codes With Extended Min-Sum Algorithm. - Chia-Lung Lin; Shu-Wen Tu; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Design considerations and clinical applications of closed-loop neural disorder control SoCs. - Chung-Yu Wu; Cheng-Hsiang Cheng; Yi-Huan Ou-Yang; Chiung-Ghu Chen; Wei-Ming Chen; Ming-Dou Ker; Chen-Yi Lee; Sheng-Fu Liang; Fu-Zen Shaw (ASP-DAC, 2017)

Sample Preparation on Micro-Electrode-Dot-Array Digital Microfluidic Biochips. - Zipeng Li; Kelvin Yi-Tse Lai; Krishnendu Chakrabarty; Tsung-Yi Ho; Chen-Yi Lee (ISVLSI, 2017)

A 41.3/26.7 pJ per Neuron Weight RBM Processor Supporting On-Chip Learning/Inference for IoT Applications. - Chang-Hung Tsai; Wan-Ju Yu; Wing Hung Wong; Chen-Yi Lee (IEEE J. Solid State Circuits, 2017)

Droplet Size-Aware and Error-Correcting Sample Preparation Using Micro-Electrode-Dot-Array Digital Microfluidic Biochips. - Zipeng Li; Kelvin Yi-Tse Lai; Krishnendu Chakrabarty; Tsung-Yi Ho; Chen-Yi Lee (IEEE Trans. Biomed. Circuits Syst., 2017)

Droplet Size-Aware High-Level Synthesis for Micro-Electrode-Dot-Array Digital Microfluidic Biochips. - Zipeng Li; Kelvin Yi-Tse Lai; Po-Hsien Yu; Krishnendu Chakrabarty; Tsung-Yi Ho; Chen-Yi Lee (IEEE Trans. Biomed. Circuits Syst., 2017)

An Improved DPA Countermeasure Based on Uniform Distribution Random Power Generator for IoT Applications. - Szu-Chi Chung; Chun-Yuan Yu; Sung-Shine Lee; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Diabetic Retinopathy Detection Based on Deep Convolutional Neural Networks. - Yi-Wei Chen; Tung-Yu Wu; Wing Hung Wong; Chen-Yi Lee (ICASSP, 2018)

Correlation-Based Face Detection for Recognizing Faces in Videos. - Heng-Wei Hsu; Tung-Yu Wu; Wing Hung Wong; Chen-Yi Lee (ICASSP, 2018)

Confnet: Predict with Confidence. - Sheng Wan; Tung-Yu Wu; Wing Hung Wong; Chen-Yi Lee (ICASSP, 2018)

A 1.86mJ/Gb/query bit-plane payload machine learning processor in 90nm CMOS. - Fang-Ju Ku; Tung-Yu Wu; Yen-Chin Liao; Hsie-Chia Chang; Wing Hung Wong; Chen-Yi Lee (VLSI-DAT, 2018)

A Fully Integrated 16-Channel Closed-Loop Neural-Prosthetic CMOS SoC With Wireless Power and Bidirectional Data Telemetry for Real-Time Efficient Human Epileptic Seizure Control. - Cheng-Hsiang Cheng; Ping-Yuan Tsai; Tzu-Yi Yang; Wan-Hsueh Cheng; Ting-Yang Yen; Zhicong Luo; Xin-Hong Qian; Zhi-Xin Chen; Tzu-Han Lin; Wei-Hong Chen; Wei-Ming Chen; Sheng-Fu Liang; et al. (IEEE J. Solid State Circuits, 2018)

Efficient and Adaptive Error Recovery in a Micro-Electrode-Dot-Array Digital Microfluidic Biochip. - Zipeng Li; Kelvin Yi-Tse Lai; John McCrone; Po-Hsien Yu; Krishnendu Chakrabarty; Miroslav Pajic; Tsung-Yi Ho; Chen-Yi Lee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Structural and Functional Test Methods for Micro-Electrode-Dot-Array Digital Microfluidic Biochips. - Zipeng Li; Kelvin Yi-Tse Lai; Po-Hsien Yu; Krishnendu Chakrabarty; Tsung-Yi Ho; Chen-Yi Lee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Sample preparation for multiple-reactant bioassays on micro-electrode-dot-array biochips. - Tung-Che Liang; Yun-Sheng Chan; Tsung-Yi Ho; Krishnendu Chakrabarty; Chen-Yi Lee (ASP-DAC, 2019)

Short-time-span EEG-based personalized emotion recognition with deep convolutional neural network. - Kit Hwa Cheah; Humaira Nisar; Vooi Voon Yap; Chen-Yi Lee (ICSIPA, 2019)

Joint Capacitive Sensing and Frequency Selection for Fast Medical Tests. - Yun-Sheng Chan; Kuan-Yu Lung; Yun-Ming Wang; Chen-Yi Lee (ISCAS, 2019)

Centralized State Sensing using Sensor Array on Wearable Device. - Eugene Lee 001; Tsu-Jui Hsu; Chen-Yi Lee (ISCAS, 2019)

A Lightweight 1.16 pJ/bit Processor for the Authenticated Encryption Scheme KetjeSR. - Yun-Wen Lu; Antoon Purnal; Simon Vandenhende; Chen-Yi Lee; Ingrid Verbauwhede; Hsie-Chia Chang (VLSI-DAT, 2019)

Micro-Electrode-Dot-Array Digital Microfluidic Biochips: Technology, Design Automation, and Test Techniques. - Zhanwei Zhong; Zipeng Li; Krishnendu Chakrabarty; Tsung-Yi Ho; Chen-Yi Lee (IEEE Trans. Biomed. Circuits Syst., 2019)

QuatNet: Quaternion-Based Head Pose Estimation With Multiregression Loss. - Heng-Wei Hsu; Tung-Yu Wu; Sheng Wan; Wing Hung Wong; Chen-Yi Lee (IEEE Trans. Multim., 2019)

NeuralScale: Efficient Scaling of Neurons for Resource-Constrained Deep Neural Networks. - Eugene Lee 001; Chen-Yi Lee (CVPR, 2020)

Meta-rPPG: Remote Heart Rate Estimation Using a Transductive Meta-learner. - Eugene Lee 001; Evan Chen; Chen-Yi Lee (ECCV (27), 2020)

Miniaturized Intracerebral Potential Recorder for Long-Term Local Field Potential of Deep Brain Signals. - Yi-Hui Wu; Yi-Huan Ou-Yang; Chiung-Chu Chen; Chen-Yi Lee; Chung-Yu Wu; Ming-Dou Ker (EMBC, 2020)

Cross-Domain Adaptation for Biometric Identification Using Photoplethysmogram. - Eugene Lee 001; Annie Ho; Yi-Ting Wang; Cheng-Han Huang; Chen-Yi Lee (ICASSP, 2020)

An Area-Efficient High-Throughput SM4 Accelerator with SCA-Countermeasure for TV Applications. - Wei Chiang; Hsie-Chia Chang; Chen-Yi Lee (ISCAS, 2020)

Convolutional neural networks for classification of music-listening EEG: comparing 1D convolutional kernels with 2D kernels and cerebral laterality of musical influence. - Kit Hwa Cheah; Humaira Nisar; Vooi Voon Yap; Chen-Yi Lee (Neural Comput. Appl., 2020)

A Real-Time Wearable Assist System for Upper Extremity Throwing Action Based on Accelerometers. - Kuang-Yow Lian; Wei-Hsiu Hsu; Deepak Balram; Chen-Yi Lee (Sensors, 2020)

Multitarget Sample Preparation Using MEDA Biochips. - Tung-Che Liang; Yun-Sheng Chan; Tsung-Yi Ho; Krishnendu Chakrabarty; Chen-Yi Lee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Feature Consistency Training With JPEG Compressed Images. - Sheng Wan; Tung-Yu Wu; Heng-Wei Hsu; Wing Hung Wong; Chen-Yi Lee (IEEE Trans. Circuits Syst. Video Technol., 2020)

FADE: Feature Aggregation for Depth Estimation With Multi-View Stereo. - Hsiao-Chien Yang; Po-Heng Chen; Kuan-Wen Chen; Chen-Yi Lee; Yong-Sheng Chen (IEEE Trans. Image Process., 2020)

Few-Shot and Continual Learning with Attentive Independent Mechanisms. - Eugene Lee 001; Cheng-Han Huang; Chen-Yi Lee (ICCV, 2021)

Fast Adaption for Multi Motor Anomaly Detection via Meta Learning and deep unsupervised learning. - Yi-Cheng Yu; Shang-Wen Chuang; Hong-Han Shuai; Chen-Yi Lee (ISIE, 2022)

Bio-Chips for Fast Medial Tests Networks. - Chen-Yi Lee (VLSI-DAT, 2022)

A Traveling-Wave Dielectrophoresis Bio-Chip for Cell Manipulation in Standard CMOS Process. - Yun-Sheng Chan; Ting-Ting Hsu; Yi-Po Chen; Hsu-Min Wu; Yun-Ming Wang; Chen-Yi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Programmable Bio-Chip With Adaptive Pattern-Control Micro-Electrode-Dot-Array. - Yun-Sheng Chan; Chen-Yi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Pattern-Control Digital Microfluidic Bio-Chip for Fast Thermal Cycle in Nucleic Acid Amplification Tests. - Yun-Sheng Chan; Jiajie Diao; Chen-Yi Lee (ISCAS, 2023)

A Stack-Based In-Pixel Storage Circuit for SPAD Photon Counting. - Tzu-Yun Huang; Hsi-Hao Huang; Chun-Hsien Liu; Sheng-Di Lin; Chen-Yi Lee (ISCAS, 2023)

Self-Restoring and Low-Jitter Circuits for High Timing-Resolution SPAD Sensing Applications. - Hsi-Hao Huang; Chun-Hsien Liu; Tzu-Yun Huang; Sheng-Di Lin; Chen-Yi Lee (ISCAS, 2023)

Cross-Resolution Flow Propagation for Foveated Video Super-Resolution. - Eugene Lee 001; Lien-Feng Hsu; Evan Chen; Chen-Yi Lee (WACV, 2023)

A 460 800 Pixels CMOS Capacitive Sensor Array With Programmable Fusion Pixels and Noise Canceling for Life Science Applications. - Lin-Hung Lai; Wen-Yue Lin; Yu-Wei Lu; Heng-Yu Lui; Shinsuke Yoshida; Shih-Hwa Chiou; Chen-Yi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A Programmable CMOS Dielectrophoresis Array Chip with 128 × 128 Electrodes for Cell Manipulation. - Wen-Yue Lin; Lin-Hung Lai; Yi-Wei Lin; Chen-Yi Lee (ISCAS, 2024)

A 2.56-µs Dynamic Range, 31.25-ps Resolution 2-D Vernier Digital-to-Time Converter (DTC) for Cell-Monitoring. - Heng-Yu Liu; Lin-Hung Lai; Wen-Yue Lin; Yu-Wei Lu; Yi-Wei Lin; Chen-Yi Lee (ISCAS, 2024)

Industrial Semiconductor GPT: A Question-and-Answer System that Provides Professional Advice and Problem-Solving Methods for Semiconductor and Factory Equipment and Process. - Yi-Cheng Yu; Cheng-Fu Liou; Shang-Wen Chuang; Chen-Yi Lee (ISIE, 2024)

A Low-Latency Data Compressor for SPAD-Based Depth Estimation Systems. - Tzu-Yun Huang; Po-Ya Huang; Chen-Yi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A Dual-Mode Readout Circuit for SPAD Imaging Applications. - Hsi-Hao Huang; Tzu-Yun Huang; Chun-Hsien Liu; Sheng-Di Lin; Chen-Yi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

M*: On-Chip Microfluidic Operations With A-Star for Portable Diagnostics. - Cheng-Hsuan Hsieh; Eugene Lee 001; Peng Hsien Chi; Jiajie Diao; Chen-Yi Lee (ICASSP, 2025)

Multiple Sampling and Pixel-Wise Accumulation in CMOS Capacitive Sensor Array System for Real-Time Droplet Analysis. - Lin-Hung Lai; Wen-Yue Lin; Yu-Chen Hung; Yu-Hsian Wang; Hsi-Hao Huang; Chen-Yi Lee (ISCAS, 2025)

Smart Pattern Generation on Programmable Dielectrophoresis Array Chip for Single Particle Manipulation. - Yu-Hsiang Wang; Wen-Yue Lin; Lin-Hung Lai; Chen-Yi Lee (ISCAS, 2025)

A Programmable CMOS DEP Chip for Cell Manipulation. - Wen-Yue Lin; Lin-Hung Lai; Yi-Wei Lin; Chen-Yi Lee (IEEE Trans. Biomed. Circuits Syst., 2025)