Skipper: a microarchitecture for exploiting control-flow independence. - Chen-Yong Cher; T. N. Vijaykumar (MICRO, 2001)

VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power. - Hai Li 001; Chen-Yong Cher; T. N. Vijaykumar; Kaushik Roy 001 (MICRO, 2003)

Software prefetching for mark-sweep garbage collection: hardware analysis and software redesign. - Chen-Yong Cher; Antony L. Hosking; T. N. Vijaykumar (ASPLOS, 2004)

Combined circuit and architectural level variable supply-voltage scaling for low power. - Hai Li 001; Chen-Yong Cher; Kaushik Roy 001; T. N. Vijaykumar (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Do Trace Cache, Value Prediction and Prefetching Improve SMT Throughput?. - Chen-Yong Cher; Il Park 001; T. N. Vijaykumar (ARCS, 2006)

An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget. - Canturk Isci; Alper Buyuktosunoglu; Chen-Yong Cher; Pradip Bose; Margaret Martonosi (MICRO, 2006)

Thermal-aware task scheduling at the system software level. - Jeonghwan Choi; Chen-Yong Cher; Hubertus Franke; Hendrik F. Hamann; Alan J. Weger; Pradip Bose (ISLPED, 2007)

Variation-aware thermal characterization and management of multi-core architectures. - Eren Kursun; Chen-Yong Cher (ICCD, 2008)

Software-Controlled Priority Characterization of POWER5 Processor. - Carlos Boneti; Francisco J. Cazorla; Roberto Gioiosa; Alper Buyuktosunoglu; Chen-Yong Cher; Mateo Valero (ISCA, 2008)

Cell GC: using the cell synergistic processor as a garbage collection coprocessor. - Chen-Yong Cher; Michael Gschwind (VEE, 2008)

Temperature Variation Characterization and Thermal Management of Multicore Architectures. - Eren Kursun; Chen-Yong Cher (IEEE Micro, 2009)

Power and thermal characterization of POWER6 system. - Víctor Jiménez; Francisco J. Cazorla; Roberto Gioiosa; Mateo Valero; Carlos Boneti; Eren Kursun; Chen-Yong Cher; Canturk Isci; Alper Buyuktosunoglu; Pradip Bose (PACT, 2010)

Performance and power evaluation of an in-line accelerator. - Alejandro Rico; Jeff H. Derby; Robert K. Montoye; Timothy H. Heil; Chen-Yong Cher; Pradip Bose (Conf. Computing Frontiers, 2010)

Power-efficient, reliable microprocessor architectures: modeling and design methods. - Pradip Bose; Alper Buyuktosunoglu; Chen-Yong Cher; John A. Darringer; Meeta Sharma Gupta; Hendrik F. Hamann; Hans M. Jacobson; Prabhakar Kudva; Eren Kursun; Niti Madan; Indira Nair; Jude A. Rivers; et al. (ACM Great Lakes Symposium on VLSI, 2010)

A wire-speed powerTM processor: 2.3GHz 45nm SOI with 16 cores and 64 threads. - Charles L. Johnson; David H. Allen; Jeffrey D. Brown; Steve Vanderwiel; Russ Hoover; Heather D. Achilles; Chen-Yong Cher; George A. May; Hubertus Franke; Jimi Xenidis; Claude Basso (ISSCC, 2010)

Trends and techniques for energy efficient architectures. - Víctor Jiménez; Roberto Gioiosa; Eren Kursun; Francisco J. Cazorla; Chen-Yong Cher; Alper Buyuktosunoglu; Pradip Bose; Mateo Valero (VLSI-SoC, 2010)

Characterizing Power and Temperature Behavior of POWER6-Based System. - Víctor Jiménez; Francisco J. Cazorla; Roberto Gioiosa; Mateo Valero; Carlos Boneti; Eren Kursun; Chen-Yong Cher; Canturk Isci; Alper Buyuktosunoglu; Pradip Bose (IEEE J. Emerg. Sel. Topics Circuits Syst., 2011)

Exploring the effects of on-chip thermal variation on high-performance multicore architectures. - Chen-Yong Cher; Eren Kursun (ACM Trans. Archit. Code Optim., 2011)

An information-theoretic framework for optimal temperature sensor allocation and full-chip thermal monitoring. - Huapeng Zhou; Xin Li 001; Chen-Yong Cher; Eren Kursun; Haifeng Qian; Shi-Chune Yao (DAC, 2012)

Quantitative evaluation of soft error injection techniques for robust system design. - Hyungmin Cho; Shahrzad Mirkhani; Chen-Yong Cher; Jacob A. Abraham; Subhasish Mitra (DAC, 2013)

Innovative practices session 11C: Resilience. - Chen-Yong Cher; Mohan J. Kumar (VTS, 2013)

Innovative practices session 7C: Self-calibration & trimming. - Chen-Yong Cher; Yiorgos Makris; C. Thibeault; Alan J. Drake (VTS, 2013)

Design for low power and power management in IBM Blue Gene/Q. - Krishnan Sugavanam; Chen-Yong Cher; John A. Gunnels; Ruud A. Haring; Philip Heidelberger; Hans M. Jacobson; Moyra K. McManus; D. P. Paulsen; David L. Satterfield; Yutaka Sugawara; Robert Walkup (IBM J. Res. Dev., 2013)

SMT Malleability in IBM POWER5 and POWER6 Processors. - Alessandro Morari; Carlos Boneti; Francisco J. Cazorla; Roberto Gioiosa; Chen-Yong Cher; Alper Buyuktosunoglu; Pradip Bose; Mateo Valero (IEEE Trans. Computers, 2013)

Soft Error Resiliency Characterization on IBM BlueGene/Q Processor. - Chen-Yong Cher; K. Paul Muller; Ruud A. Haring; David L. Satterfield; Thomas E. Musta; Thomas Gooding; Kristan D. Davis; Marc Boris Dombrowa; Gerard V. Kopcsay; Robert M. Senger; Yutaka Sugawara; Krishnan Sugavanam (ASP-DAC, 2014)

Cross layer resiliency in real world. - Vikas Chandra; Subhasish Mitra; Chen-Yong Cher; Silvia Melitta Müller (DATE, 2014)

Soft error resiliency characterization and improvement on IBM BlueGene/Q processor using accelerated proton irradiation. - Chen-Yong Cher; K. Paul Muller; Ruud A. Haring; David L. Satterfield; Thomas E. Musta; Thomas Gooding; Kristan D. Davis; Marc Boris Dombrowa; Gerard V. Kopcsay; Robert M. Senger; Yutaka Sugawara; Krishnan Sugavanam (ITC, 2014)

Understanding Soft Error Resiliency of Blue Gene/Q Compute Chip through Hardware Proton Irradiation and Software Fault Injection. - Chen-Yong Cher; Meeta Sharma Gupta; Pradip Bose; K. Paul Muller (SC, 2014)

A System Software Approach to Proactive Memory-Error Avoidance. - Carlos H. A. Costa; Yoonho Park; Bryan S. Rosenburg; Chen-Yong Cher; Kyung Dong Ryu (SC, 2014)

The resilience wall: Cross-layer solution strategies. - Subhasish Mitra; Pradip Bose; Eric Cheng; Chen-Yong Cher; Hyungmin Cho; Rajiv V. Joshi; Young Moon Kim; Charles R. Lefurgy; Yanjing Li; Kenneth P. Rodbell; Kevin Skadron; James H. Stathis; et al. (VLSI-DAT, 2014)

Understanding soft errors in uncore components. - Hyungmin Cho; Chen-Yong Cher; Thomas Shepherd; Subhasish Mitra (DAC, 2015)

Efficient soft error vulnerability estimation of complex designs. - Shahrzad Mirkhani; Subhasish Mitra; Chen-Yong Cher; Jacob A. Abraham (DATE, 2015)

Experience report: An application-specific checkpointing technique for minimizing checkpoint corruption. - Guanpeng Li; Karthik Pattabiraman; Chen-Yong Cher; Pradip Bose (ISSRE, 2015)

Understanding the propagation of transient errors in HPC applications. - Rizwan A. Ashraf; Roberto Gioiosa; Gokcen Kestor; Ronald F. DeMara; Chen-Yong Cher; Pradip Bose (SC, 2015)

Active Memory Cube: A processing-in-memory architecture for exascale systems. - Ravi Nair; Samuel Antão; Carlo Bertolli; Pradip Bose; José R. Brunheroto; Tong Chen 001; Chen-Yong Cher; Carlos H. A. Costa; J. Doi; Constantinos Evangelinos; Bruce M. Fleischer; Thomas W. Fox; et al. (IBM J. Res. Dev., 2015)

Clear: cross-layer exploration for architecting resilience combining hardware and software techniques to tolerate soft errors in processor cores. - Eric Cheng; Shahrzad Mirkhani; Lukasz G. Szafaryn; Chen-Yong Cher; Hyungmin Cho; Kevin Skadron; Mircea R. Stan; Klas Lilja; Jacob A. Abraham; Pradip Bose; Subhasish Mitra (DAC, 2016)

Measurement-Driven Methodology for Evaluating Processor Heterogeneity Options for Power-Performance Efficiency. - William J. Song; Alper Buyuktosunoglu; Chen-Yong Cher; Pradip Bose (ISLPED, 2016)

Understanding error propagation in GPGPU applications. - Guanpeng Li; Karthik Pattabiraman; Chen-Yong Cher; Pradip Bose (SC, 2016)

BRAVO: Balanced Reliability-Aware Voltage Optimization. - Karthik Swaminathan; Nandhini Chandramoorthy; Chen-Yong Cher; Ramon Bertran; Alper Buyuktosunoglu; Pradip Bose (HPCA, 2017)

Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights. - Eric Cheng; Jacob A. Abraham; Pradip Bose; Alper Buyuktosunoglu; Keith A. Campbell; Deming Chen; Chen-Yong Cher; Hyungmin Cho; Binh Q. Le; Klas Lilja; Shahrzad Mirkhani; Kevin Skadron; et al. (ICCD, 2017)

System-Level Effects of Soft Errors in Uncore Components. - Hyungmin Cho; Eric Cheng; Thomas Shepherd; Chen-Yong Cher; Subhasish Mitra (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience). - Eric Cheng; Shahrzad Mirkhani; Lukasz G. Szafaryn; Chen-Yong Cher; Hyungmin Cho; Kevin Skadron; Mircea R. Stan; Klas Lilja; Jacob A. Abraham; Pradip Bose; Subhasish Mitra (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

CLEAR Cross-Layer Resilience: A Retrospective. - Eric Cheng; Hyungmin Cho; Shahrzad Mirkhani; Lukasz G. Szafaryn; Jacob A. Abraham; Pradip Bose; Chen-Yong Cher; Klas Lilja; Kevin Skadron; Mircea Stan; Subhasish Mitra (IEEE Des. Test, 2025)