DPALS: A dynamic programming-based algorithm for two-level approximate logic synthesis. - Chen Zou 001; Weikang Qian; Jie Han 001 (ASICON, 2015)

UDP: a programmable accelerator for extract-transform-load workloads and more. - Yuanwei Fang; Chen Zou 001; Aaron J. Elmore; Andrew A. Chien (MICRO, 2017)

Motion artifact removal based on periodical property for ECG monitoring with wearable systems. - Chen Zou 001; Yajie Qin; Chenglu Sun; Wei Li 134; Wei Chen 015 (Pervasive Mob. Comput., 2017)

Accelerating Raw Data Analysis with the ACCORDA Software and Hardware Architecture. - Yuanwei Fang; Chen Zou 001; Andrew A. Chien (Proc. VLDB Endow., 2019)

A Novel Heuristic Search Method for Two-Level Approximate Logic Synthesis. - Sanbao Su; Chen Zou 001; Weijiang Kong; Jie Han 001; Weikang Qian (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Computational Storage to Increase the Analysis Capability of Tier-2 HEP Data Sites. - Chen Zou 001; Andrew A. Chien; Robert W. Gardner; Ilija Vukotic (CLUSTER, 2021)

PSACS: Highly-Parallel Shuffle Accelerator on Computational Storage. - Chen Zou 001; Hui Zhang 033; Andrew A. Chien; Yang-Seok Ki (ICCD, 2021)

ASSASIN: Architecture Support for Stream Computing to Accelerate Computational Storage. - Chen Zou 001; Andrew A. Chien (MICRO, 2022)

VarVE: Bringing SIMD Performance to Variable-Width Values. - Chen Zou 001; Andrew A. Chien (ICCD, 2024)