A high throughput in-loop de-blocking filter supporting H.264/AVC BP/MP/HP video coding. - Cheng-An Chien; Hsiu-Cheng Chang; Jiun-In Guo (APCCAS, 2008)

A dynamic quality-scalable H.264 video encoder chip. - Hsiu-Cheng Chang; Yao-Chang Yang; Jia-Wei Chen; Ching-Lung Su; Cheng-An Chien; Jiun-In Guo; Jinn-Shyan Wang (ASP-DAC, 2009)

A Dynamic Quality-scalable H.264 Video Encoder. - Hsiu-Cheng Chang; Jia-Wei Chen; Yao-Chang Yang; Cheng-An Chien; Tzu-Chun Chang; Jinn-Shyan Wang; Jiun-In Guo (ISCAS, 2009)

A Multi-standard Video Decoder for High Definition Video Applications. - Cheng-An Chien; Chih-Da Chien; Jui-Chin Chu; Jiun-In Guo; Ching-Hwa Cheng (ISCAS, 2009)

A High Throughput Deblocking Filter Design Supporting Multiple Video Coding Standards. - Cheng-An Chien; Hsiu-Cheng Chang; Jiun-In Guo (ISCAS, 2009)

A 252Kgates/4.9Kbytes SRAM/71mW multistandard video decoder for high definition video applications. - Chih-Da Chien; Cheng-An Chien; Jui-Chin Chu; Jiun-In Guo; Ching-Hwa Cheng (ACM Trans. Design Autom. Electr. Syst., 2009)

A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video. - Cheng-An Chien; Yao-Chang Yang; Hsiu-Cheng Chang; Jia-Wei Chen; Cheng-Yen Chang; Jiun-In Guo; Jinn-Shyan Wang; Ching-Hwa Cheng (ASP-DAC, 2011)

Dual-phase pipeline circuit design automation with a built-in performance adjusting mechanism. - Yu-Tzu Tsai; Cheng-Chih Tsai; Cheng-An Chien; Ching-Hwa Cheng; Jiun-In Guo (ASP-DAC, 2011)

A low-power management technique for high-performance domino circuits. - Yu-Tzu Tsai; Cheng-Chih Tsai; Cheng-An Chien; Ching-Hwa Cheng; Jiun-In Guo (ASP-DAC, 2011)

An inter-frame/inter-view cache architecture design for multi-view video decoders. - Jui-Sheng Lee; Sheng-Han Wang; Chih-Tai Chou; Cheng-An Chien; Hsiu-Cheng Chang; Jiun-In Guo (APSIPA, 2012)

A two level mode decision algorithm for H.264 high profile intra encoding. - Cheng-Yen Chang; Cheng-An Chien; Hsiu-Cheng Chang; Jia-Wei Chen; Jiun-In Guo (ISCAS, 2012)

3D depth map generation for embedded stereo applications. - Jui-Sheng Lee; Guo-An Jian; Cheng-An Chien; Peng-Sheng Chen; Jiun-In Guo (VCIP, 2012)

A Verification-Aware Design Methodology for Thread Pipelining Parallelization. - Guo-An Jian; Cheng-An Chien; Peng-Sheng Chen; Jiun-In Guo (IEICE Trans. Inf. Syst., 2012)

High efficiency data access system architecture for deblocking filter supporting multiple video coding standards. - Cheng-An Chien; Guo-An Jian; Hsiu-Cheng Chang; Kuan-Hung Chen; Jiun-In Guo (IEEE Trans. Consumer Electron., 2012)

A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS. - Tay-Jyi Lin; Cheng-An Chien; Pei-Yao Chang; Ching-Wen Chen; Po-Hao Wang; Ting-Yu Shyu; Chien-Yung Chou; Shien-Chun Luo; Jiun-In Guo; Tien-Fu Chen; Gene C. H. Chuang; Yuan-Hua Chu; et al. (ISSCC, 2013)

A view scalable multi-view video decoder system. - Jui-Sheng Lee; Yuan-Hsiang Miao; Cheng-An Chien; Hsiu-Cheng Chang; Jiun-In Guo (VLSI-DAT, 2013)

Real-Time 3D Depth Generation for Stereoscopic Video Applications with Thread-Level Superscalar-Pipeline Parallelization. - Guo-An Jian; Cheng-An Chien; Peng-Sheng Chen; Jiun-In Guo (J. Signal Process. Syst., 2013)

A 360-degree panoramic video system design. - Kai-Chen Huang; Po-Yu Chien; Cheng-An Chien; Hsiu-Cheng Chang; Jiun-In Guo (VLSI-DAT, 2014)