A high speed and energy efficient full adder design using complementary & level restoring carry logic. - Jin-Fa Lin; Yin-Tsung Hwang; Ming-Hwa Sheu; Cheng-Che Ho (ISCAS, 2006)

A Novel High-Speed and Energy Efficient 10-Transistor Full Adder Design. - Jin-Fa Lin; Yin-Tsung Hwang; Ming-Hwa Sheu; Cheng-Che Ho (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)