A 0.22 nJ/b/iter 0.13 μm turbo decoder chip using inter-block permutation interleaver. - Cheng-Chi Wong; Cheng-Hao Tang; Ming-Wei Lai; Yan-Xiu Zheng; Chien-Ching Lin; Hsie-Chia Chang; Chen-Yi Lee; Yu.-T. Su (CICC, 2007)

A multiple code-rate turbo decoder based on reciprocal dual trellis architecture. - Chen-Yang Lin; Cheng-Chi Wong; Hsie-Chia Chang (ISCAS, 2010)

Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture. - Cheng-Chi Wong; Ming-Wei Lai; Chien-Ching Lin; Hsie-Chia Chang; Chen-Yi Lee (IEEE J. Solid State Circuits, 2010)

Reconfigurable Turbo Decoder With Parallel Architecture for 3GPP LTE System. - Cheng-Chi Wong; Hsie-Chia Chang (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

High-Efficiency Processing Schedule for Parallel Turbo Decoders Using QPP Interleaver. - Cheng-Chi Wong; Hsie-Chia Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

A 40 nm 535 Mbps Multiple Code-Rate Turbo Decoder Chip Using Reciprocal Dual Trellis. - Chen-Yang Lin; Cheng-Chi Wong; Hsie-Chia Chang (IEEE J. Solid State Circuits, 2013)

An Area Efficient Radix-4 Reciprocal Dual Trellis Architecture for a High-Code-Rate Turbo Decoder. - Chen-Yang Lin; Cheng-Chi Wong; Hsie-Chia Chang (IEEE Trans. Circuits Syst. II Express Briefs, 2015)