Optimal Supply Voltage Assignment under Timing, Power and Area Constraints. - Hsi-An Chien; Cheng-Chiang Lin; Hsin-Hsiung Huang; Tsai-Ming Hsieh (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Wire Planning for Electromigration and Interference Avoidance in Analog Circuits. - Hsin-Hsiung Huang; Jui-Hung Hung; Cheng-Chiang Lin; Tsai-Ming Hsieh (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)