A 64-MHz∼640-MHz 64-phase clock generator. - Hong-Yi Huang; Jen-Chieh Liu; Shi-Jia Sun; Cheng-Hao Fu; Kuo-Hsing Cheng (DDECS, 2014)

Worst-Case and Average-Case Hardness of Hypercycle and Database Problems. - Cheng-Hao Fu; Andrea Lincoln; Rene Reyes (ICALP, 2025)