A 2.25 TOPS/W Fully-Integrated Deep CNN Learning Processor with On-Chip Training. - Cheng-Hsun Lu; Yi-Chung Wu; Chia-Hsiang Yang (A-SSCC, 2019)

Arvon: A Heterogeneous SiP Integrating a 14nm FPGA and Two 22nm 1.8TFLOPS/W DSPs with 1.7Tbps/mm2 AIB 2.0 Interface to Provide Versatile Workload Acceleration. - Wei Tang 010; Sung-Gun Cho; Tim Tri Hoang; Jacob Botimer; Wei Qiang Zhu; Ching-Chi Chang; Cheng-Hsun Lu; Junkang Zhu; Yaoyu Tao; Tianyu Wei; Naomi Kavi Motwani; Mani Yalamanchi; et al. (VLSI Technology and Circuits, 2023)

An 11.4mm2 40.2Gbps 17.4pJ/b/Iteration Soft-Decision Open Forward Error Correction Decoder for Optical Communications. - Cheng-Hsun Lu; Wei Tang; Jiyoon Han; Zhengya Zhang (VLSI Technology and Circuits, 2024)

Arvon: A Heterogeneous System-in-Package Integrating FPGA and DSP Chiplets for Versatile Workload Acceleration. - Wei Tang 010; Sung-Gun Cho; Tim Tri Hoang; Jacob Botimer; Wei Qiang Zhu; Ching-Chi Chang; Cheng-Hsun Lu; Junkang Zhu; Yaoyu Tao; Tianyu Wei; Naomi Kavi Motwani; Mani Yalamanchi; et al. (IEEE J. Solid State Circuits, 2024)

TetriX: Flexible Architecture and Optimal Mapping for Tensorized Neural Network Processing. - Jie-Fang Zhang; Cheng-Hsun Lu; Zhengya Zhang (IEEE Trans. Computers, 2024)