Simultaneous driver and wire sizing for performance and power optimization. - Jason Cong; Cheng-Kok Koh (IEEE Trans. Very Large Scale Integr. Syst., 1994)

Bounded-skew clock and Steiner routing under Elmore delay. - Jason Cong; Andrew B. Kahng; Cheng-Kok Koh; Chung-Wen Albert Tsao (ICCAD, 1995)

Minimum-Cost Bounded-Skew Clock Routing. - Jason Cong; Cheng-Kok Koh (ISCAS, 1995)

Simultaneous buffer and wire sizing for performance and power optimization. - Jason Cong; Cheng-Kok Koh; Kwok-Shing Leung (ISLPED, 1996)

Performance optimization of VLSI interconnect layout. - Jason Cong; Lei He 001; Cheng-Kok Koh; Patrick H. Madden (Integr., 1996)

Global interconnect sizing and spacing with consideration of coupling capacitance. - Jason Cong; Lei He 001; Cheng-Kok Koh; David Zhigang Pan (ICCAD, 1997)

Interconnect layout optimization under higher-order RLC model. - Jason Cong; Cheng-Kok Koh (ICCAD, 1997)

Interconnect design for deep submicron ICs. - Jason Cong; David Zhigang Pan; Lei He 001; Cheng-Kok Koh; Kei-Yong Khoo (ICCAD, 1997)

Bounded-skew clock and Steiner routing. - Jason Cong; Andrew B. Kahng; Cheng-Kok Koh; Chung-Wen Albert Tsao (ACM Trans. Design Autom. Electr. Syst., 1998)

Power minimization by simultaneous dual-Vth assignment and gate-sizing. - Liqiong Wei; Kaushik Roy 001; Cheng-Kok Koh (CICC, 2000)

Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures. - Cheng-Kok Koh; Patrick H. Madden (ACM Great Lakes Symposium on VLSI, 2000)

Stochastic Wire-Length and Delay Distribution of 3-Dimensional Circuits. - Rongtian Zhang; Kaushik Roy 001; Cheng-Kok Koh; David B. Janes (ICCAD, 2000)

Frequency Domain Analysis of Switching Noise on Power Supply Network. - Shiyou Zhao; Kaushik Roy 001; Cheng-Kok Koh (ICCAD, 2000)

A Twisted Bundle Layout Structure for Minimizing Inductive Coupling Noise. - Guoan Zhong; Cheng-Kok Koh; Kaushik Roy 001 (ICCAD, 2000)

Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family. - Alexandre Solomatnikov; Kaushik Roy 001; Cheng-Kok Koh; Dinesh Somasekhar (ICCD, 2000)

Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Sub-Micron CMOS Circuits. - Shiyou Zhao; Kaushik Roy 001; Cheng-Kok Koh (ICCD, 2000)

Routability-driven repeater block planning for interconnect-centric floorplanning. - Probir Sarkar; Vivek Sundararaman; Cheng-Kok Koh (ISPD, 2000)

Efficient balance-and-truncate model reduction for large scale systems. - V. Balakrishnan 001; Q. Su; Cheng-Kok Koh (ACC, 2001)

Exploring SOI Device Structures and Interconnect Architectures for 3-Dimensional Integration. - Rongtian Zhang; Kaushik Roy 001; Cheng-Kok Koh; David B. Janes (DAC, 2001)

Repeater block planning under simultaneous delay and transition time constraints. - Probir Sarkar; Cheng-Kok Koh (DATE, 2001)

Short-circuit power analysis of an inverter driving an RLC load. - Rui Wang; Kaushik Roy 001; Cheng-Kok Koh (ISCAS (4), 2001)

Power trends and performance characterization of 3-dimensional integration. - Rongtian Zhang; Kaushik Roy 001; Cheng-Kok Koh; David B. Janes (ISCAS (4), 2001)

Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications. - Naran Sirisantana; Aiqun Cao; Shawn Davidson; Cheng-Kok Koh; Kaushik Roy 001 (ISLPED, 2001)

Decoupling capacitance allocation for power supply noise suppression. - Shiyou Zhao; Kaushik Roy 001; Cheng-Kok Koh (ISPD, 2001)

Power Trends and Performance Characterization of 3-Dimensional Integration for Future Technology Generations. - Rongtian Zhang; Kaushik Roy 001; Cheng-Kok Koh; David B. Janes (ISQED, 2001)

Interconnect sizing and spacing with consideration of couplingcapacitance. - Jason Cong; Lei He 001; Cheng-Kok Koh; David Zhigang Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Interconnect layout optimization under higher order RLC model forMCM designs. - Jason Cong; Cheng-Kok Koh; Patrick H. Madden (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Routability-driven repeater block planning for interconnect-centricfloorplanning. - Probir Sarkar; Cheng-Kok Koh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

A factorization-based framework for passivity-preserving model reduction of RLC systems. - Q. Su; Venkataramanan Balakrishnan; Cheng-Kok Koh (DAC, 2002)

Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods. - Yiran Chen 001; Venkataramanan Balakrishnan; Cheng-Kok Koh; Kaushik Roy 001 (DATE, 2002)

Flip-Flop and Repeater Insertion for Early Interconnect Planning. - Ruibing Lu; Guoan Zhong; Cheng-Kok Koh; Kai-Yuan Chao (DATE, 2002)

Exact Closed Form Formula for Partial Mutual Inductances of On-Chip Interconnects. - Guoan Zhong; Cheng-Kok Koh (ICCD, 2002)

Synthesis of Selectively Clocked Skewed Logic Circuits. - Aiqun Cao; Naran Sirisantana; Cheng-Kok Koh; Kaushik Roy 001 (ISQED, 2002)

Power Supply Noise Suppression via Clock Skew Scheduling. - Wai-Ching Douglas Lam; Cheng-Kok Koh; Chung-Wen Albert Tsao (ISQED, 2002)

Efficient Approximate Balanced Truncation of General Large-Scale RLC Systems via Krylov Methods. - Q. Su; Venkataramanan Balakrishnan; Cheng-Kok Koh (ASP-DAC/VLSI Design, 2002)

Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement. - Shiyou Zhao; Kaushik Roy 001; Cheng-Kok Koh (ASP-DAC/VLSI Design, 2002)

Decoupling capacitance allocation and its application topower-supply noise-aware floorplanning. - Shiyou Zhao; Kaushik Roy 001; Cheng-Kok Koh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

UST/DME: a clock tree router for general skew constraints. - Chung-Wen Albert Tsao; Cheng-Kok Koh (ACM Trans. Design Autom. Electr. Syst., 2002)

Integer linear programming-based synthesis of skewed logic circuits. - Aiqun Cao; Naran Sirisantana; Cheng-Kok Koh; Kaushik Roy 001 (ASP-DAC, 2003)

A metric for analyzing effective on-chip inductive coupling. - Guoan Zhong; Cheng-Kok Koh; Kaushik Roy 001 (ASP-DAC, 2003)

An adaptive window-based susceptance extraction and its efficient implementation. - Guoan Zhong; Cheng-Kok Koh; Venkataramanan Balakrishnan; Kaushik Roy 001 (DAC, 2003)

Interconnect Planning with Local Area Constrained Retiming. - Ruibing Lu; Cheng-Kok Koh (DATE, 2003)

SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips. - Ruibing Lu; Cheng-Kok Koh (ICCAD, 2003)

Performance Optimization of Latency Insensitive Systems Through Buffer Queue Sizing of Communication Channels. - Ruibing Lu; Cheng-Kok Koh (ICCAD, 2003)

Non-Crossing OBDDs for Mapping to Regular Circuit Structures. - Aiqun Cao; Cheng-Kok Koh (ICCD, 2003)

Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors. - Yiran Chen 001; Kaushik Roy 001; Cheng-Kok Koh (ISLPED, 2003)

Clock Scheduling for Power Supply Noise Suppression using Genetic Algorithm with Selective Gene Therapy. - Wai-Ching Douglas Lam; Cheng-Kok Koh; Chung-Wen Albert Tsao (ISQED, 2003)

On-chip interconnect modeling by wire duplication. - Guoan Zhong; Cheng-Kok Koh; Kaushik Roy 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor. - Yiran Chen 001; Kaushik Roy 001; Cheng-Kok Koh (ASP-DAC, 2004)

A high performance bus communication architecture through bus splitting. - Ruibing Lu; Cheng-Kok Koh (ASP-DAC, 2004)

Post-layout logic optimization of domino circuits. - Aiqun Cao; Cheng-Kok Koh (DAC, 2004)

Passivity-preserving model reduction via a computationally efficient project-and-balance scheme. - Ngai Wong 001; Venkataramanan Balakrishnan; Cheng-Kok Koh (DAC, 2004)

A fast Newton/Smith algorithm for solving algebraic Riccati equations and its application in model order reduction. - Ngai Wong 001; Venkataramanan Balakrishnan; Cheng-Kok Koh; Tung-Sang Ng (ICASSP (5), 2004)

Fast simulation of VLSI interconnects. - Jitesh Jain; Cheng-Kok Koh; Venkataramanan Balakrishnan (ICCAD, 2004)

Recursive bisection based mixed block placement. - Ateen Khatkhate; Chen Li 004; Ameya R. Agnihotri; Mehmet Can Yildiz; Satoshi Ono; Cheng-Kok Koh; Patrick H. Madden (ISPD, 2004)

A Performance and Power Co-optimization Approach for Modern Processors. - Yongxin Zhu 001; Weng-Fai Wong; Cheng-Kok Koh (CIT, 2005)

Post-layout logic duplication for synthesis of domino circuits with complex gates. - Aiqun Cao; Ruibing Lu; Cheng-Kok Koh (ASP-DAC, 2005)

Process variation robust clock tree routing. - Wai-Ching Douglas Lam; Cheng-Kok Koh (ASP-DAC, 2005)

Compact and stable modeling of partial inductance and reluctance matrices. - Hong Li; Venkataramanan Balakrishnan; Cheng-Kok Koh; Guoan Zhong (ASP-DAC, 2005)

Floorplan management: incremental placement for gate sizing and buffer insertion. - Chen Li 004; Cheng-Kok Koh; Patrick H. Madden (ASP-DAC, 2005)

Improving the scalability of SAMBA bus architecture. - Ruibing Lu; Aiqun Cao; Cheng-Kok Koh (ASP-DAC, 2005)

3D module placement for congestion and power noise reduction. - Jacob R. Minz; Sung Kyu Lim; Cheng-Kok Koh (ACM Great Lakes Symposium on VLSI, 2005)

Statistical based link insertion for robust clock network design. - Wai-Ching Douglas Lam; Jitesh Jain; Cheng-Kok Koh; Venkataramanan Balakrishnan; Yiran Chen 001 (ICCAD, 2005)

Cascaded carry-select adder (C2SA): a new structure for low-power CSA design. - Yiran Chen 001; Hai Li 001; Kaushik Roy 001; Cheng-Kok Koh (ISLPED, 2005)

Mixed block placement via fractional cut recursive bisection. - Ameya R. Agnihotri; Satoshi Ono; Chen Li 004; Mehmet Can Yildiz; Ateen Khatkhate; Cheng-Kok Koh; Patrick H. Madden (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Synthesis of skewed logic circuits. - Aiqun Cao; Naran Sirisantana; Cheng-Kok Koh; Kaushik Roy 001 (ACM Trans. Design Autom. Electr. Syst., 2005)

Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors. - Yiran Chen 001; Kaushik Roy 001; Cheng-Kok Koh (IEEE Trans. Very Large Scale Integr. Syst., 2005)

SASIMI: sparsity-aware simulation of interconnect-dominated circuits with non-linear devices. - Jitesh Jain; Stephen Cauley; Cheng-Kok Koh; Venkataramanan Balakrishnan (ASP-DAC, 2006)

SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design. - Hai Li 001; Yiran Chen 001; Kaushik Roy 001; Cheng-Kok Koh (ASP-DAC, 2006)

Adaptive admittance-based conductor meshing for interconnect analysis. - Ya-Chi Yang; Cheng-Kok Koh; Venkataramanan Balakrishnan (ASP-DAC, 2006)

Clock Generation and Distribution Using Traveling-Wave Oscillators with Reflection and Regeneration. - Ruilin Wang; Cheng-Kok Koh; Byunghoo Jung; William J. Chappell (CICC, 2006)

Stable and compact inductance modeling of 3-D interconnect structures. - Hong Li; Venkataramanan Balakrishnan; Cheng-Kok Koh (ICCAD, 2006)

Performance analysis of latency-insensitive systems. - Ruibing Lu; Cheng-Kok Koh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Two Algorithms for Fast and Accurate Passivity-Preserving Model Order Reduction. - Ngai Wong 001; Venkataramanan Balakrishnan; Cheng-Kok Koh; Tung-Sang Ng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Exact and numerically stable closed-form expressions for potential coefficients of rectangular conductors. - Jitesh Jain; Cheng-Kok Koh; Venkataramanan Balakrishnan (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

Postlayout optimization for synthesis of Domino circuits. - Aiqun Cao; Ruibing Lu; Chen Li 004; Cheng-Kok Koh (ACM Trans. Design Autom. Electr. Syst., 2006)

A fast band-matching technique for interconnect inductance modeling. - Hong Li; Jitesh Jain; Cheng-Kok Koh; Venkataramanan Balakrishnan (ICCAD, 2007)

A frequency-domain technique for statistical timing analysis of clock meshes. - Ruilin Wang; Cheng-Kok Koh (ICCAD, 2007)

VOSCH: Voltage scaled cache hierarchies. - Weng-Fai Wong; Cheng-Kok Koh; Yiran Chen 001; Hai Li 001 (ICCD, 2007)

Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI. - Yiran Chen 001; Hai Li 001; Jing Li 073; Cheng-Kok Koh (ISLPED, 2007)

Efficient Analysis of Large-Scale Power Grids Based on a Compact Cholesky Factorization. - Hong Li; Jitesh Jain; Venkataramanan Balakrishnan; Cheng-Kok Koh (ISQED, 2007)

Recursive Function Smoothing of Half-Perimeter Wirelength for Analytical Placement. - Chen Li 004; Cheng-Kok Koh (ISQED, 2007)

Statistical Timing Analysis Considering Spatial Correlations. - Hong Li; Cheng-Kok Koh; Venkataramanan Balakrishnan; Yiran Chen 001 (ISQED, 2007)

Routability-Driven Placement and White Space Allocation. - Chen Li 004; Min Xie 004; Cheng-Kok Koh; Jason Cong; Patrick H. Madden (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Corrections to "Exact and Numerically Stable Closed-Form Expressions for Potential Coefficients of Rectangular Conductors". - Jitesh Jain; Cheng-Kok Koh; Venkataramanan Balakrishnan (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips. - Ruibing Lu; Aiqun Cao; Cheng-Kok Koh (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Guiding global placement with wire density. - Kalliopi Tsota; Cheng-Kok Koh; Venkataramanan Balakrishnan (ICCAD, 2008)

A fast band matching technique for impedance extraction. - Jitesh Jain; Hong Li; Cheng-Kok Koh; Venkataramanan Balakrishnan (ISCAS, 2008)

Optimal post-routing redundant via insertion. - Kuang-Yao Lee; Cheng-Kok Koh; Ting-Chi Wang; Kai-Yuan Chao (ISPD, 2008)

Fast and Optimal Redundant Via Insertion. - Kuang-Yao Lee; Cheng-Kok Koh; Ting-Chi Wang; Kai-Yuan Chao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Global Interconnect Planning. - Cheng-Kok Koh; Evangeline F. Y. Young; Yao-Wen Chang (Handbook of Algorithms for Physical Design Automation, 2008)

A direct integral-equation solver of linear complexity for large-scale 3D capacitance and impedance extraction. - Wenwen Chai; Dan Jiao; Cheng-Kok Koh (DAC, 2009)

A study of routability estimation and clustering in placement. - Kalliopi Tsota; Cheng-Kok Koh; Venkataramanan Balakrishnan (ICCAD, 2009)

The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies. - Cheng-Kok Koh; Weng-Fai Wong; Yiran Chen 001; Hai Li 001 (ICCD, 2009)

Tolerating process variations in large, set-associative caches: The buddy cache. - Cheng-Kok Koh; Weng-Fai Wong; Yiran Chen 001; Hai Li 001 (ACM Trans. Archit. Code Optim., 2009)

Gated Decap: Gate Leakage Control of On-Chip Decoupling Capacitors in Scaled Technologies. - Yiran Chen 001; Hai Li 001; Kaushik Roy 001; Cheng-Kok Koh (IEEE Trans. Very Large Scale Integr. Syst., 2009)

PEDS: Passivity enforcement for descriptor systems via Hamiltonian-symplectic matrix pencil perturbation. - Yuanzhe Wang; Zheng Zhang 005; Cheng-Kok Koh; Grantham K. H. Pang; Ngai Wong 001 (ICCAD, 2010)

How to Improve Your Google Ranking: Myths and Reality. - Ao-Jan Su; Y. Charlie Hu; Aleksandar Kuzmanovic; Cheng-Kok Koh (Web Intelligence, 2010)

A Parallel Direct Solver for the Simulation of Large-Scale Power/Ground Networks. - Stephen Cauley; Venkataramanan Balakrishnan; Cheng-Kok Koh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Optimal Double Via Insertion With On-Track Preference. - Kuang-Yao Lee; Ting-Chi Wang; Cheng-Kok Koh; Kai-Yuan Chao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance. - Yiran Chen 001; Hai Li 001; Cheng-Kok Koh; Guangyu Sun 003; Jing Li 073; Yuan Xie 001; Kaushik Roy 001 (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Simultaneous redundant via insertion and line end extension for yield optimization. - Shing-Tung Lin; Kuang-Yao Lee; Ting-Chi Wang; Cheng-Kok Koh; Kai-Yuan Chao (ASP-DAC, 2011)

Processor caches with multi-level spin-transfer torque ram cells. - Yiran Chen 001; Weng-Fai Wong; Hai Li 001; Cheng-Kok Koh (ISLPED, 2011)

Synthesis of low power clock trees for handling power-supply variations. - Shashank Bujimalla; Cheng-Kok Koh (ISPD, 2011)

Cross link insertion for improving tolerance to variations in clock network synthesis. - Tarun Mittal; Cheng-Kok Koh (ISPD, 2011)

Finite difference schemes for heat conduction analysis in integrated circuit design and manufacturing. - Yijiang Shen; Ngai Wong 001; Edmund Y. Lam; Cheng-Kok Koh (Int. J. Circuit Theory Appl., 2011)

A parallel branch-and-cut approach for detailed placement. - Stephen Cauley; Venkataramanan Balakrishnan; Y. Charlie Hu; Cheng-Kok Koh (ACM Trans. Design Autom. Electr. Syst., 2011)

A fast maze-free routing congestion estimator with hybrid unilateral monotonic routing. - Wen-Hao Liu 001; Yih-Lang Li; Cheng-Kok Koh (ICCAD, 2012)

Mixed integer programming models for detailed placement. - Shuai Li; Cheng-Kok Koh (ISPD, 2012)

A size scaling approach for mixed-size placement. - Kalliopi Tsota; Cheng-Kok Koh; Venkataramanan Balakrishnan (ISPD, 2012)

A two-dimensional domain decomposition technique for the simulation of quantum-scale devices. - Stephen Cauley; Venkataramanan Balakrishnan; Gerhard Klimeck; Cheng-Kok Koh (J. Comput. Phys., 2012)

Guest Editorial Special Section on the 2011 International Symposium on Physical Design. - Jiang Hu; Cheng-Kok Koh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

A Quadratic Eigenvalue Solver of Linear Complexity for 3-D Electromagnetics-Based Analysis of Large-Scale Integrated Circuits. - Jongwon Lee; Duo Chen; Venkataramanan Balakrishnan; Cheng-Kok Koh; Dan Jiao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Passivity Enforcement for Descriptor Systems Via Matrix Pencil Perturbation. - Yuanzhe Wang; Zheng Zhang 005; Cheng-Kok Koh; Guoyong Shi; Grantham K. H. Pang; Ngai Wong 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Optimization of placement solutions for routability. - Wen-Hao Liu 001; Cheng-Kok Koh; Yih-Lang Li (DAC, 2013)

A 3D-point-cloud feature for human-pose estimation. - Kai-Chi Chan; Cheng-Kok Koh; C. S. George Lee (ICRA, 2013)

Using action classification for human-pose estimation. - Kai-Chi Chan; Cheng-Kok Koh; C. S. George Lee (IROS, 2013)

Local merges for effective redundancy in clock networks. - Rickard Ewetz; Cheng-Kok Koh (ISPD, 2013)

Case study for placement solutions in ispd11 and dac12 routability-driven placement contests. - Wen-Hao Liu 001; Cheng-Kok Koh; Yih-Lang Li (ISPD, 2013)

Collaborative object tracking with motion similarity measure. - Kai-Chi Chan; Cheng-Kok Koh; C. S. George Lee (ROBIO, 2013)

On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations. - Yiran Chen 001; Weng-Fai Wong; Hai Li 001; Cheng-Kok Koh; Yaojun Zhang; Wujie Wen (ACM J. Emerg. Technol. Comput. Syst., 2013)

Analytical estimates of stress around a doubly periodic arrangement of through-silicon vias. - Anirudh Udupa; Ganesh Subbarayan; Cheng-Kok Koh (Microelectron. Reliab., 2013)

Guest editorial: Special section on cross-domain physical optimization. - Jiang Hu; Cheng-Kok Koh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Analytical placement of mixed-size circuits for better detailed-routability. - Shuai Li; Cheng-Kok Koh (ASP-DAC, 2014)

A study on the use of parallel wiring techniques for sub-20nm designs. - Rickard Ewetz; Wen-Hao Liu 001; Kai-Yuan Chao; Ting-Chi Wang; Cheng-Kok Koh (ACM Great Lakes Symposium on VLSI, 2014)

A TSV-cross-link-based approach to 3D-clock network synthesis for improved robustness. - Rickard Ewetz; Anirudh Udupa; Ganesh Subbarayan; Cheng-Kok Koh (ACM Great Lakes Symposium on VLSI, 2014)

Selecting best viewpoint for human-pose estimation. - Kai-Chi Chan; Cheng-Kok Koh; C. S. George Lee (ICRA, 2014)

MIP-based detailed placer for mixed-size circuits. - Shuai Li; Cheng-Kok Koh (ISPD, 2014)

Guest Editorial Special Section on Contemporary and Emerging Issues in Physical Design. - Cheng-Kok Koh; Chin Ngai Sze (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

A 3-D-Point-Cloud System for Human-Pose Estimation. - Kai-Chi Chan; Cheng-Kok Koh; C. S. George Lee (IEEE Trans. Syst. Man Cybern. Syst., 2014)

How to Improve Your Search Engine Ranking: Myths and Reality. - Ao-Jan Su; Y. Charlie Hu; Aleksandar Kuzmanovic; Cheng-Kok Koh (ACM Trans. Web, 2014)

Fast clock skew scheduling based on sparse-graph algorithms. - Rickard Ewetz; Shankarshana Janarthanan; Cheng-Kok Koh (ASP-DAC, 2015)

Construction of reconfigurable clock trees for MCMM designs. - Rickard Ewetz; Shankarshana Janarthanan; Cheng-Kok Koh (DAC, 2015)

Human-pose estimation with neural-network realization. - Kai-Chi Chan; Cheng-Kok Koh; C. S. George Lee (IROS, 2015)

A Useful Skew Tree Framework for Inserting Large Safety Margins. - Rickard Ewetz; Cheng-Kok Koh (ISPD, 2015)

Rubik: Unlocking the Power of Locality and End-point Flexibility in Cloud Scale Load Balancing. - Rohan Gandhi; Y. Charlie Hu; Cheng-Kok Koh; Hongqiang Harry Liu; Ming Zhang 005 (USENIX ATC, 2015)

Cost-Effective Robustness in Clock Networks Using Near-Tree Structures. - Rickard Ewetz; Cheng-Kok Koh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

MCMM clock tree optimization based on slack redistribution using a reduced slack graph. - Rickard Ewetz; Cheng-Kok Koh (ASP-DAC, 2016)

Construction of Latency-Bounded Clock Trees. - Rickard Ewetz; Chuan Yean Tan; Cheng-Kok Koh (ISPD, 2016)

Construction of Reconfigurable Clock Trees for MCMM Designs Using Mode Separation and Scenario Compression. - Rickard Ewetz; Cheng-Kok Koh (ACM Trans. Design Autom. Electr. Syst., 2016)

An Automatic Design of Factors in a Human-Pose Estimation System Using Neural Networks. - Kai-Chi Chan; Cheng-Kok Koh; C. S. George Lee (IEEE Trans. Syst. Man Cybern. Syst., 2016)

Delay-driven layer assignment for advanced technology nodes. - Szu-Yuan Han; Wen-Hao Liu 001; Rickard Ewetz; Cheng-Kok Koh; Kai-Yuan Chao; Ting-Chi Wang (ASP-DAC, 2017)

Saath: Speeding up CoFlows by Exploiting the Spatial Dimension. - Akshay Jajoo; Rohan Gandhi; Y. Charlie Hu; Cheng-Kok Koh (CoNEXT, 2017)

Clock Tree Construction based on Arrival Time Constraints. - Rickard Ewetz; Cheng-Kok Koh (ISPD, 2017)

Fast clock scheduling and an application to clock tree synthesis. - Rickard Ewetz; Cheng-Kok Koh (Integr., 2017)

Clustering of flip-flops for useful-skew clock tree synthesis. - Chuan Yean Tan; Rickard Ewetz; Cheng-Kok Koh (ASP-DAC, 2018)

Scalable Construction of Clock Trees With Useful Skew and High Timing Quality. - Rickard Ewetz; Cheng-Kok Koh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

A Scalable Buffer Queue Sizing Algorithm for Latency Insensitive Systems. - Supriyo Maji; Cheng-Kok Koh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

A Scalable, Memory-Efficient Algorithm for Minimum Cycle Mean Calculation in Directed Graphs. - Supriyo Maji; Cheng-Kok Koh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Real-Time 3-D Thermal Simulation of Advanced Packages via Generative Adversarial Networks. - Seunghyun Hwang; Michael Joseph Smith; Vinicius C. Do Nascimento; Qiang Qiu 001; Cheng-Kok Koh; Ganesh Subbarayan; Dan Jiao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)