60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration. - Chi-Hang Chan; Yan Zhu 001; Cheng Li 010; Wai-Hong Zhang; Iok-Meng Ho; Lai Wei; Seng-Pan U; Rui Paulo Martins (IEEE J. Solid State Circuits, 2017)

Missing-Code-Occurrence Probability Calibration Technique for DAC Nonlinearity With Supply and Reference Circuit Analysis in a SAR ADC. - Guan-Cheng Wang 002; Cheng Li 010; Yan Zhu 001; Jianyu Zhong; Yan Lu 002; Chi-Hang Chan; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 0.19 mm2 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS. - Yan Zhu 001; Chi-Hang Chan; Zi-Hao Zheng; Cheng Li 010; Jianyu Zhong; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Analysis of Reference Error in High-Speed SAR ADCs With Capacitive DAC. - Cheng Li 010; Chi-Hang Chan; Yan Zhu 001; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A Highly Efficient 165-GHz 4FSK 17-Gb/s Transceiver System With Frequency Overlapping Architecture in 65-nm CMOS. - Hamidreza Afzal; Cheng Li 010; Omeed Momeni (IEEE J. Solid State Circuits, 2023)