Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip. - Cheng Liu 008; Lei Zhang 008; Yinhe Han 001; Xiaowei Li 001 (ASP-DAC, 2011)

A resilient on-chip router design through data path salvaging. - Cheng Liu 008; Lei Zhang 008; Yinhe Han 001; Xiaowei Li 001 (ASP-DAC, 2011)

A Soft Coarse-Grained Reconfigurable Array Based High-level Synthesis Methodology: Promoting Design Productivity and Exploring Extreme FPGA Frequency. - Cheng Liu 008; Colin Yu Lin; Hayden Kwok-Hay So (FCCM, 2013)

Probabilistic Scheduling of Scientific Workflows in Dynamic Cloud Environments. - Amelie Chi Zhou; Bingsheng He; Cheng Liu 008 (CoRR, 2013)

RevivePath: Resilient Network-on-Chip Design Through Data Path Salvaging of Router. - Yinhe Han 001; Cheng Liu 008; Hang Lu; Wen-Bo Li; Lei Zhang 008; Xiaowei Li 001 (J. Comput. Sci. Technol., 2013)

Automatic Soft CGRA Overlay Customization for High-Productivity Nested Loop Acceleration on FPGAs. - Cheng Liu 008; Hayden Kwok-Hay So (FCCM, 2015)

QuickDough: A rapid FPGA loop accelerator design framework using soft CGRA overlay. - Cheng Liu 008; Ho-Cheung Ng; Hayden Kwok-Hay So (FPT, 2015)

Automatic Nested Loop Acceleration on FPGAs Using Soft CGRA Overlay. - Cheng Liu 008; Ho-Cheung Ng; Hayden Kwok-Hay So (CoRR, 2015)

Economizing TSV Resources in 3-D Network-on-Chip Design. - Ying Wang 001; Yinhe Han 001; Lei Zhang 008; Binzhang Fu; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

FPGA Overlays. - Hayden Kwok-Hay So; Cheng Liu 008 (FPGAs for Software Programmers, 2016)

A Soft Processor Overlay with Tightly-coupled FPGA Accelerator. - Ho-Cheung Ng; Cheng Liu 008; Hayden Kwok-Hay So (CoRR, 2016)

Monetary Cost Optimizations for Hosting Workflow-as-a-Service in IaaS Clouds. - Amelie Chi Zhou; Bingsheng He; Cheng Liu 008 (IEEE Trans. Cloud Comput., 2016)

A Virtual Channel Allocation Algorithm for NoC. - Dongxing Bao; Xiaoming Li 002; Yizong Xin; Jiuru Yang; Xiangshi Ren; Fangfa Fu; Cheng Liu 008 (EAI Endorsed Trans. Ambient Syst., 2017)

FCN-engine: accelerating deconvolutional layers in classic CNN processors. - Dawen Xu 002; Kaijie Tu; Ying Wang 001; Cheng Liu 008; Bingsheng He; Huawei Li 001 (ICCAD, 2018)

Resilient Neural Network Training for Accelerators with Computing Errors. - Dawen Xu 002; KouZi Xing; Cheng Liu 008; Ying Wang 001; Yulin Dai; Long Cheng 003; Huawei Li 001; Lei Zhang 008 (ASAP, 2019)

Exploring emerging CNFET for efficient last level cache design. - Dawen Xu 002; Li Li; Ying Wang 001; Cheng Liu 008; Huawei Li 001 (ASP-DAC, 2019)

InS-DLA: An In-SSD Deep Learning Accelerator for Near-Data Processing. - Shengwen Liang; Ying Wang 001; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001 (FPL, 2019)

OBFS: OpenCL Based BFS Optimizations on Software Programmable FPGAs. - Cheng Liu 008; Xinyu Chen 001; Bingsheng He; Xiaofei Liao; Ying Wang 001; Lei Zhang 008 (FPT, 2019)

Squeezing the Last MHz for CNN Acceleration on FPGAs. - Li Li; Dawen Xu 002; Kouzi Xing; Cheng Liu 008; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ITC-Asia, 2019)

A Survey on Graph Processing Accelerators: Challenges and Opportunities. - Chuangyi Gui; Long Zheng 003; Bingsheng He; Cheng Liu 008; Xinyu Chen 001; Xiaofei Liao; Hai Jin 001 (J. Comput. Sci. Technol., 2019)

Emerging Hardware Technologies. - Xuntao Cheng; Cheng Liu 008; Bingsheng He (Encyclopedia of Big Data Technologies, 2019)

Persistent Fault Analysis of Neural Networks on FPGA-based Acceleration System. - Dawen Xu 002; Ziyang Zhu; Cheng Liu 008; Ying Wang 001; Huawei Li 001; Lei Zhang 008; Kwang-Ting Cheng (ASAP, 2020)

BitPruner: Network Pruning for Bit-serial Accelerators. - Xiandong Zhao; Ying Wang 001; Cheng Liu 008; Cong Shi 003; Kaijie Tu; Lei Zhang 008 (DAC, 2020)

CNT-Cache: an Energy-Efficient Carbon Nanotube Cache with Adaptive Encoding. - Dawen Xu 002; Kexin Chu; Cheng Liu 008; Ying Wang 001; Lei Zhang 008; Huawei Li 001 (DATE, 2020)

Multi-task Scheduling for PIM-based Heterogeneous Computing System. - Dawen Xu 002; Cheng Chu; Cheng Liu 008; Ying Wang 001; Xianzhong Zhou; Lei Zhang 008; Huaguo Liang; Huawei Li 001 (ACM Great Lakes Symposium on VLSI, 2020)

DeepBurning-GL: an Automated Framework for Generating Graph Neural Network Accelerators. - Shengwen Liang; Cheng Liu 008; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ICCAD, 2020)

A Hybrid Computing Architecture for Fault-tolerant Deep Learning Accelerators. - Dawen Xu 002; Cheng Chu; Qianlong Wang; Cheng Liu 008; Ying Wang 001; Lei Zhang 008; Huaguo Liang; Kwang-Ting Cheng (ICCD, 2020)

Energy Efficient In-memory Integer Multiplication Based on Racetrack Memory. - Tao Luo 014; Wei Zhang 012; Bingsheng He; Cheng Liu 008; Douglas L. Maskell (ICDCS, 2020)

Linear Symmetric Quantization of Neural Networks for Low-precision Integer Hardware. - Xiandong Zhao; Ying Wang 001; Xuyi Cai; Cheng Liu 008; Lei Zhang 008 (ICLR, 2020)

Accelerating Generative Neural Networks on Unmodified Deep Learning Processors - A Software Approach. - Dawen Xu 002; Cheng Liu 008; Ying Wang 001; Kaijie Tu; Bingsheng He; Lei Zhang 008 (IEEE Trans. Computers, 2020)

VADER: Leveraging the Natural Variation of Hardware to Enhance Adversarial Attack. - Hao Lv; Bing Li 017; Ying Wang 001; Cheng Liu 008; Lei Zhang 008 (ASP-DAC, 2021)

GCiM: A Near-Data Processing Accelerator for Graph Construction. - Lei He 016; Cheng Liu 008; Ying Wang 001; Shengwen Liang; Huawei Li 001; Xiaowei Li 001 (DAC, 2021)

TARe: Task-Adaptive in-situ ReRAM Computing for Graph Learning. - Yintao He; Ying Wang 001; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001 (DAC, 2021)

Network-on-Interposer Design for Agile Neural-Network Processor Chip Customization. - Mengdi Wang; Ying Wang 001; Cheng Liu 008; Lei Zhang 008 (DAC, 2021)

MT-DLA: An Efficient Multi-Task Deep Learning Accelerator Design. - Mengdi Wang; Bing Li 017; Ying Wang 001; Cheng Liu 008; Xiaohan Ma; Xiandong Zhao; Lei Zhang 008 (ACM Great Lakes Symposium on VLSI, 2021)

PicoVO: A Lightweight RGB-D Visual Odometry Targeting Resource-Constrained IoT Devices. - Yuquan He; Ying Wang 001; Cheng Liu 008; Lei Zhang 008 (ICRA, 2021)

NASA: Accelerating Neural Network Design with a NAS Processor. - Xiaohan Ma; Chang Si; Ying Wang 001; Cheng Liu 008; Lei Zhang 008 (ISCA, 2021)

CHaNAS: coordinated search for network architecture and scheduling policy. - Weiwei Chen; Ying Wang 001; Gangliang Lin; Chengsi Gao; Cheng Liu 008; Lei Zhang 008 (LCTES, 2021)

GLIST: Towards In-Storage Graph Learning. - Cangyuan Li; Ying Wang 001; Cheng Liu 008; Shengwen Liang; Huawei Li 001; Xiaowei Li 001 (USENIX ATC, 2021)

Energy-Efficient Accelerator Design for Deformable Convolution Networks. - Dawen Xu 002; Cheng Chu; Cheng Liu 008; Ying Wang 001; Huawei Li 001; Xiaowei Li 001; Kwang-Ting Cheng (CoRR, 2021)

Taming Process Variations in CNFET for Efficient Last Level Cache Design. - Dawen Xu 002; Zhuangyu Feng; Cheng Liu 008; Li Li; Ying Wang 001; Yuanqing Cheng; Huawei Li 001; Xiaowei Li 001 (CoRR, 2021)

EnGN: A High-Throughput and Energy-Efficient Accelerator for Large Graph Neural Networks. - Shengwen Liang; Ying Wang 001; Cheng Liu 008; Lei He 016; Huawei Li 001; Dawen Xu 002; Xiaowei Li 001 (IEEE Trans. Computers, 2021)

Network-Aware Locality Scheduling for Distributed Data Operators in Data Centers. - Long Cheng 003; Ying Wang 001; Qingzhi Liu; Dick H. J. Epema; Cheng Liu 008; Ying Mao 001; John Murphy 001 (IEEE Trans. Parallel Distributed Syst., 2021)

R2F: A Remote Retraining Framework for AIoT Processors With Computing Errors. - Dawen Xu 002; Meng He 012; Cheng Liu 008; Ying Wang 001; Long Cheng 003; Huawei Li 001; Xiaowei Li 001; Kwang-Ting Cheng (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System. - Dawen Xu 002; Ziyang Zhu; Cheng Liu 008; Ying Wang 001; Shuang Zhao; Lei Zhang 008; Huaguo Liang; Huawei Li 001; Kwang-Ting Cheng (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Processing-in-SRAM acceleration for ultra-low power visual 3D perception. - Yuquan He; Songyun Qu; Gangliang Lin; Cheng Liu 008; Lei Zhang 008; Ying Wang 001 (DAC, 2022)

VStore: in-storage graph based vector search accelerator. - Shengwen Liang; Ying Wang 001; Ziming Yuan; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001 (DAC, 2022)

Winograd convolution: a perspective from fault tolerance. - Xinghua Xue; Haitong Huang; Cheng Liu 008; Tao Luo 014; Lei Zhang 008; Ying Wang 001 (DAC, 2022)

NoCeption: A Fast PPA Prediction Framework for Network-on-Chips Using Graph Neural Network. - Fuping Li; Ying Wang 001; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001 (DATE, 2022)

Reexamining CGRA Memory Sub-system for Higher Memory Utilization and Performance. - Lei Dai; Ying Wang 001; Cheng Liu 008; Fuping Li; Huawei Li 001; Xiaowei Li 001 (ICCD, 2022)

Special Session: Fault-Tolerant Deep Learning: A Hierarchical Perspective. - Cheng Liu 008; Zhen Gao 005; Siting Liu 001; Xuefei Ning; Huawei Li 001; Xiaowei Li 001 (VTS, 2022)

Fault-Tolerant Deep Learning: A Hierarchical Perspective. - Cheng Liu 008; Zhen Gao 005; Siting Liu 001; Xuefei Ning; Huawei Li 001; Xiaowei Li 001 (CoRR, 2022)

Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems. - Benjamin Chen Ming Choong; Tao Luo 014; Cheng Liu 008; Bingsheng He; Wei Zhang 012; Joey Tianyi Zhou (J. Syst. Archit., 2022)

HyCA: A Hybrid Computing Architecture for Fault-Tolerant Deep Learning. - Cheng Liu 008; Cheng Chu; Dawen Xu 002; Ying Wang 001; Qianlong Wang; Huawei Li 001; Xiaowei Li 001; Kwang-Ting Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Taming Process Variations in CNFET for Efficient Last-Level Cache Design. - Dawen Xu 002; Zhuangyu Feng; Cheng Liu 008; Li Li; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design - A Self-Test, Self-Diagnosis, and Self-Repair-Based Approach - Xiaowei Li 001; Guihai Yan; Cheng Liu 008 (Springer, 2023)

Layer-Puzzle: Allocating and Scheduling Multi-task on Multi-core NPUs by Using Layer Heterogeneity. - Chengsi Gao; Ying Wang 001; Cheng Liu 008; Mengdi Wang; Weiwei Chen; Yinhe Han 001; Lei Zhang 008 (DATE, 2023)

DeepBurning-MixQ: An Open Source Mixed-Precision Neural Network Accelerator Design Framework for FPGAs. - Erjing Luo; Haitong Huang; Cheng Liu 008; Guoyu Li; Bing Yang; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ICCAD, 2023)

MA-BERT: Towards Matrix Arithmetic-only BERT Inference by Eliminating Complex Non-Linear Functions. - Neo Wei Ming; Zhehui Wang; Cheng Liu 008; Rick Siow Mong Goh; Tao Luo 014 (ICLR, 2023)

Reliability Analysis of Vision Transformers. - Xinghua Xue; Cheng Liu 008; Ying Wang 001; Bing Yang; Tao Luo 014; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (CoRR, 2023)

ApproxABFT: Approximate Algorithm-Based Fault Tolerance for Vision Transformers. - Xinghua Xue; Cheng Liu 008; Haitong Huang; Ying Wang 001; Bing Yang; Tao Luo 014; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (CoRR, 2023)

MRFI: An Open Source Multi-Resolution Fault Injection Framework for Neural Network Processing. - Haitong Huang; Cheng Liu 008; Xinghua Xue; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (CoRR, 2023)

Deep Learning Accelerator in Loop Reliability Evaluation for Autonomous Driving. - Haitong Huang; Cheng Liu 008 (CoRR, 2023)

Cross-Layer Optimization for Fault-Tolerant Deep Learning. - Qing Zhang; Cheng Liu 008; Bo Liu 018; Haitong Huang; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (CoRR, 2023)

A Framework for Neural Network Architecture and Compile Co-optimization. - Weiwei Chen; Ying Wang 001; Ying Xu; Chengsi Gao; Cheng Liu 008; Lei Zhang 008 (ACM Trans. Embed. Comput. Syst., 2023)

On-Line Fault Protection for ReRAM-Based Neural Networks. - Wen Li; Ying Wang 001; Cheng Liu 008; Yintao He; Lian Liu; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Computers, 2023)

S$^{2}$ Loop: A Lightweight Spectral-Spatio Loop Closure Detector for Resource-Constrained Platforms. - Yuquan He; Long Zhang; Cheng Liu 008; Lei Zhang 008; Ying Wang 001 (IEEE Robotics Autom. Lett., 2023)

Variation Enhanced Attacks Against RRAM-Based Neuromorphic Computing System. - Hao Lv; Bing Li 017; Lei Zhang 008; Cheng Liu 008; Ying Wang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Network Pruning for Bit-Serial Accelerators. - Xiandong Zhao; Ying Wang 001; Cheng Liu 008; Cong Shi 003; Kaijie Tu; Lei Zhang 008 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Accelerating Deformable Convolution Networks with Dynamic and Irregular Memory Accesses. - Cheng Chu; Cheng Liu 008; Dawen Xu 002; Ying Wang 001; Tao Luo 014; Huawei Li 001; Xiaowei Li 001 (ACM Trans. Design Autom. Electr. Syst., 2023)

Statistical Modeling of Soft Error Influence on Neural Networks. - Haitong Huang; Xinghua Xue; Cheng Liu 008; Ying Wang 001; Tao Luo 014; Long Cheng 003; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Exploring Winograd Convolution for Cost-Effective Neural Network Fault Tolerance. - Xinghua Xue; Cheng Liu 008; Bo Liu 018; Haitong Huang; Ying Wang 001; Tao Luo 014; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Soft Error Reliability Analysis of Vision Transformers. - Xinghua Xue; Cheng Liu 008; Ying Wang 001; Bing Yang; Tao Luo 014; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2023)

AGC: A Unified Architecture for Accelerating K-Nearest Neighbor Graph Construction in Vector Search. - Lei Dai; Ziming Yuan; Wen Li; Shengwen Liang; Kaiwei Zou; Ying Wang 001; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001 (ICCAD, 2024)

HLSPilot: LLM-based High-Level Synthesis. - Chenwei Xiong; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001 (ICCAD, 2024)

ApproxPilot: A GNN-based Accelerator Approximation Framework. - Qing Zhang; Cheng Liu 008; Siting Liu 001; Yajuan Hui; Huawei Li 001; Xiaowei Li 001 (CoRR, 2024)

SigDLA: A Deep Learning Accelerator Extension for Signal Processing. - Fangfa Fu; Wenyu Zhang; Zesong Jiang; Zhiyu Zhu; Guoyu Li; Bing Yang; Cheng Liu 008; Liyi Xiao; Jinxiang Wang 001; Huawei Li 001; Xiaowei Li 001 (CoRR, 2024)

Graphitron: A Domain Specific Language for FPGA-based Graph Processing Accelerator Generation. - Xinmiao Zhang 004; Zheng Feng; Shengwen Liang; Xinyu Chen 001; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001 (CoRR, 2024)

IICPilot: An Intelligent Integrated Circuit Backend Design Framework Using Open EDA. - Zesong Jiang; Qing Zhang; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001 (CoRR, 2024)

MCU-MixQ: A HW/SW Co-optimized Mixed-precision Neural Network Design Framework for MCUs. - Junfeng Gong; Cheng Liu 008; Long Cheng 003; Huawei Li 001; Xiaowei Li 001 (CoRR, 2024)

DRIM-ANN: An Approximate Nearest Neighbor Search Engine based on Commercial DRAM-PIMs. - Mingkai Chen; Tianhua Han; Cheng Liu 008; Shengwen Liang; Kuai Yu; Lei Dai; Ziming Yuan; Ying Wang 001; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (CoRR, 2024)

Advancements in Accelerating Deep Neural Network Inference on AIoT Devices: A Survey. - Long Cheng 003; Yan Gu; Qingzhi Liu; Lei Yang 018; Cheng Liu 008; Ying Wang 001 (IEEE Trans. Sustain. Comput., 2024)

A Deep Reinforcement Learning-Based Preemptive Approach for Cost-Aware Cloud Job Scheduling. - Long Cheng 003; Yue Wang 073; Feng Cheng; Cheng Liu 008; Zhiming Zhao; Ying Wang 001 (IEEE Trans. Sustain. Comput., 2024)

In-Memory Wallace Tree Multipliers Based on Majority Gates Within Voltage-Gated SOT-MRAM Crossbar Arrays. - YaJuan Hui; Qingzhen Li; Leimin Wang; Cheng Liu 008; Deming Zhang; Xiangshui Miao (IEEE Trans. Very Large Scale Integr. Syst., 2024)

PDG: A Prefetcher for Dynamic Graph Updating. - Xinmiao Zhang 004; Cheng Liu 008; Jiacheng Ni; Yuanqing Cheng; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Logic-in-Memory Based on Majority Gates With Voltage-Gated SOT-MRAM Crossbar Arrays. - YaJuan Hui; Qingzhen Li; Cheng Liu 008; Deming Zhang; Xiangshui Miao (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

An Energy-Efficient In-Memory Accelerator for Graph Construction and Updating. - Mingkai Chen; Cheng Liu 008; Shengwen Liang; Lei He 016; Ying Wang 001; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

MRFI: An Open-Source Multiresolution Fault Injection Framework for Neural Network Processing. - Haitong Huang; Cheng Liu 008; Xinghua Xue; Bo Liu 018; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A Task-Adaptive In-Situ ReRAM Computing for Graph Convolutional Networks. - Yintao He; Bing Li 017; Ying Wang 001; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

HisOrder: A Historical Frontier-Aware Graph Reordering for Efficient BFS. - Xinmiao Zhang 004; Xiaorong Qin; Lei Zhang 008; Cheng Liu 008 (FCPC@PPOPP, 2025)

NeuVSA: A Unified and Efficient Accelerator for Neural Vector Search. - Ziming Yuan; Lei Dai; Wen Li; Jie Zhang 048; Shengwen Liang; Ying Wang 001; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001; Jiafeng Guo; Peng Wang 037; Renhai Chen; et al. (HPCA, 2025)

FrontOrder: Frontier-Guided Graph Reordering. - Xinmiao Zhang 004; Cheng Liu 008; Shengwen Liang; Chenwei Xiong; Yu Zhang 027; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (ICDE, 2025)

Taijigraph: an Out-Of-Core Graph Processing System Enhanced with Computational Storage. - Xinmiao Zhang 004; Cheng Liu 008; Shengwen Liang; Hayden Kwok-Hay So; Ying Wang 001; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (IPDPS, 2025)

Graphitron: A Domain Specific Language for FPGA-Based Graph Processing Accelerator Generation. - Xinmiao Zhang 004; Zheng Feng; Shengwen Liang; Xinyu Chen 001; Lei Zhang 008; Cheng Liu 008 (LCTES, 2025)

Frontier-guided Graph Reordering. - Xinmiao Zhang 004; Cheng Liu 008; Shengwen Liang; Chenwei Xiong; Yu Zhang 027; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (PPoPP, 2025)

Enabling Energy-Efficient Deployment of Large Language Models on Memristor Crossbar: A Synergy of Large and Small. - Zhehui Wang; Tao Luo 014; Cheng Liu 008; Weichen Liu; Rick Siow Mong Goh; Weng-Fai Wong (IEEE Trans. Pattern Anal. Mach. Intell., 2025)

Large Processor Chip Model. - Kaiyan Chang; Mingzhi Chen; Yunji Chen; Zhirong Chen; Dongrui Fan; Junfeng Gong; Nan Guo; Yinhe Han 001; Qinfen Hao; Shuo Hou; Xuanjing Huang 001; Pengwei Jin; et al. (CoRR, 2025)

Is quantum optimization ready? An effort towards neural network compression using adiabatic quantum computing. - Zhehui Wang; Benjamin Chen Ming Choong; Tian Huang; Daniel Gerlinghoff; Rick Siow Mong Goh; Cheng Liu 008; Tao Luo 014 (Future Gener. Comput. Syst., 2026)