A flash-based non-uniform sampling ADC enabling digital anti-aliasing filter in 65nm CMOS. - Tzu-Fan Wu; Cheng-Ru Ho; Mike Shuo-Wei Chen (CICC, 2015)

Interference-induced DCO spur mitigation for digital phase locked loop in 65-nm CMOS. - Cheng-Ru Ho; Mike Shuo-Wei Chen (ESSCIRC, 2016)

10.5 A digital PLL with feedforward multi-tone spur cancelation loop achieving <-73dBc fractional spur and <-110dBc Reference Spur in 65nm CMOS. - Cheng-Ru Ho; Mike Shuo-Wei Chen (ISSCC, 2016)

A Digital PLL With Feedforward Multi-Tone Spur Cancellation Scheme Achieving <-73 dBc Fractional Spur and <-110 dBc Reference Spur in 65 nm CMOS. - Cheng-Ru Ho; Mike Shuo-Wei Chen (IEEE J. Solid State Circuits, 2016)

A Fractional-N DPLL With Calibration-Free Multi-Phase Injection-Locked TDC and Adaptive Single-Tone Spur Cancellation Scheme. - Cheng-Ru Ho; Mike Shuo-Wei Chen (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

A Flash-Based Non-Uniform Sampling ADC With Hybrid Quantization Enabling Digital Anti-Aliasing Filter. - Tzu-Fan Wu; Cheng-Ru Ho; Mike Shuo-Wei Chen (IEEE J. Solid State Circuits, 2017)

A digital frequency synthesizer with dither-assisted pulling mitigation for simultaneous DCO and reference path coupling. - Cheng-Ru Ho; Mike Shuo-Wei Chen (ISSCC, 2018)

A fractional-N digital PLL with background-dither-noise-cancellation loop achieving <-62.5dBc worst-case near-carrier fractional spurs in 65nm CMOS. - Cheng-Ru Ho; Mike Shuo-Wei Chen (ISSCC, 2018)

8.7 A 112Gb/s ADC-DSP-Based PAM-4 Transceiver for Long-Reach Applications with >40dB Channel Loss in 7nm FinFET. - P. Mishra; A. Tan; Belal Helal; Cheng-Ru Ho; C. Loi; Jamal Riani; J. Sun; Kaizad Mistry; Karthik Raviprakash; L. Tse; M. Davoodi; M. Takefman; et al. (ISSCC, 2021)

29.4 A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional Spur. - Qiaochu Zhang; Shiyu Su; Cheng-Ru Ho; Mike Shuo-Wei Chen (ISSCC, 2021)

A Fractional-N Digital MDLL With Background Two-Point DTC Calibration. - Qiaochu Zhang; Shiyu Su; Cheng-Ru Ho; Mike Shuo-Wei Chen (IEEE J. Solid State Circuits, 2022)

A 200Gb/s Low Power DSP-Based Optical Receiver and Transmitter with Integrated TIA and Laser Drivers. - Arik Zafrany; Daniel Burgos; Li Cai; Sau Siong Chong; Colin Cramm; Sadegh Dadash; Vishal Giridharan; Vivek Gurumoorthy; Belal Helal; Cheng-Ru Ho; Amrutha Iyer; Steve Jantzi; et al. (OFC, 2023)

7.1 A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET. - J. Q. Wang; Amber Tan; Amrutha Iyer; A. Fan; A. Farhoodfar; B. Alnabulsi; B. Smith; Chang-Feng Loi; Cheng-Ru Ho; D. Cartina; Jamal Riani; J. Casanova; et al. (ISSCC, 2024)