Design of a 2.5-GHz, 3-ps jitter, 8-locking-cycle, all-digital delay-locked loop with cycle-by-cycle phase adjustment. - Chun-Yuan Cheng; Jinn-Shyan Wang; Cheng-Tai Yeh; Jenn-Shyan Sheu (VLSIC, 2012)

An ultra Low-voltage/Power-Efficient All-Digital Delay Locked Loop in 55 nm CMOS Technology. - Chun-Yuan Cheng; Jinn-Shyan Wang; Cheng-Tai Yeh (J. Circuits Syst. Comput., 2012)