A 28nm 11.2TOPS/W Hardware-Utilization-Aware Neural-Network Accelerator with Dynamic Dataflow. - Cheng-Yan Du; Chieh-Fu Tsai; Wen-Ching Chen; Liang-Yi Lin; Nian-Shyang Chang; Chun-Pin Lin; Chi-Shi Chen; Chia-Hsiang Yang (ISSCC, 2023)