Design, Fabrication, and Modeling of a Novel Dual-Axis Control Input PZT Gyroscope. - Cheng-Yang Chang; Tsung-Lin Chen (Sensors, 2017)

Task-Projected Hyperdimensional Computing for Multi-task Learning. - Cheng-Yang Chang; Yu-Chuan Chuang; An-Yeu Andy Wu (AIAI (1), 2020)

IP-HDC: Information-Preserved Hyperdimensional Computing for Multi-Task Learning. - Cheng-Yang Chang; Yu-Chuan Chuang; An-Yeu Andy Wu (SiPS, 2020)

Dynamic Hyperdimensional Computing for Improving Accuracy-Energy Efficiency Trade-Offs. - Yu-Chuan Chuang; Cheng-Yang Chang; An-Yeu Andy Wu (SiPS, 2020)

Hyperdimensional Computing with Learnable Projection for User Adaptation Framework. - Yu-Ren Hsiao; Yu-Chuan Chuang; Cheng-Yang Chang; An-Yeu Andy Wu (AIAI, 2021)

PQ-HDC: Projection-Based Quantization Scheme for Flexible and Efficient Hyperdimensional Computing. - Chi-Tse Huang; Cheng-Yang Chang; Yu-Chuan Chuang; An-Yeu Andy Wu (AIAI, 2021)

Intelligent Traffic Control System by Using Image Information. - Zong-Ming Lin; Cheng-Yang Chang; Chin-Yu Hu; Yung-Yuan Chen (CoRR, 2021)

MulTa-HDC: A Multi-Task Learning Framework For Hyperdimensional Computing. - Cheng-Yang Chang; Yu-Chuan Chuang; En-Jui Chang; An-Yeu Andy Wu (IEEE Trans. Computers, 2021)

T-EAP: Trainable Energy-Aware Pruning for NVM-based Computing-in-Memory Architecture. - Cheng-Yang Chang; Yu-Chuan Chuang; Kuang-Chao Chou; An-Yeu Wu (AICAS, 2022)

Compression-Aware Projection with Greedy Dimension Reduction for Convolutional Neural Network Activations. - Yu-Shan Tai; Chieh-Fang Teng; Cheng-Yang Chang; An-Yeu Andy Wu (ICASSP, 2022)

Learnable Mixed-precision and Dimension Reduction Co-design for Low-storage Activation. - Yu-Shan Tai; Cheng-Yang Chang; Chieh-Fang Teng; An-Yeu Andy Wu (SiPS, 2022)

BWA-NIMC: Budget-based Workload Allocation for Hybrid Near/In-Memory-Computing. - Chi-Tse Huang; Cheng-Yang Chang; Yu-Chuan Chuang; An-Yeu Andy Wu (DAC, 2023)

H-RIS: Hybrid Computing-in-Memory Architecture Exploring Repetitive Input Sharing. - Yu-Chen Chen; Cheng-Yang Chang; An-Yeu Wu (ISCAS, 2023)

DE-C3: Dynamic Energy-Aware Compression for Computing-In-Memory-Based Convolutional Neural Network Acceleration. - Guan-Wei Wu; Cheng-Yang Chang; An-Yeu Andy Wu (SOCC, 2023)

E-UPQ: Energy-Aware Unified Pruning-Quantization Framework for CIM Architecture. - Cheng-Yang Chang; Kuang-Chao Chou; Yu-Chuan Chuang; An-Yeu Wu (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)

Recent Progress and Development of Hyperdimensional Computing (HDC) for Edge Intelligence. - Cheng-Yang Chang; Yu-Chuan Chuang; Chi-Tse Huang; An-Yeu Wu (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)

Joint Optimization of Dimension Reduction and Mixed-Precision Quantization for Activation Compression of Neural Networks. - Yu-Shan Tai; Cheng-Yang Chang; Chieh-Fang Teng; Yi-Ta Chen; An-Yeu Wu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Dynamic-HDC: A Two-Stage Dynamic Inference Framework for Brain-Inspired Hyperdimensional Computing. - Yu-Chuan Chuang; Cheng-Yang Chang; An-Yeu Wu (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)

Approximate Adder Tree Design with Sparsity-Aware Encoding and In-Memory Swapping for SRAM-based Digital Compute-In-Memory Macros. - Ming-Guang Lin; Jiing-Ping Wang; Cheng-Yang Chang; An-Yeu Andy Wu (AICAS, 2024)

DIET-PIM: Dynamic Importance-based Early Termination for Energy-Efficient Processing-in-Memory Accelerator. - Cheng-Yang Chang; Chi-Tse Huang; An-Yeu Andy Wu (APCCAS, 2024)

BFP-CIM: Data-Free Quantization with Dynamic Block-Floating-Point Arithmetic for Energy-Efficient Computing-In-Memory-based Accelerator. - Cheng-Yang Chang; Chi-Tse Huang; Yu-Chuan Chuang; Kuang-Chao Chou; An-Yeu Andy Wu (ASPDAC, 2024)

BORE: Energy-Efficient Banded Vector Similarity Search with Optimized Range Encoding for Memory-Augmented Neural Network. - Chi-Tse Huang; Cheng-Yang Chang; Hsiang-Yun Cheng; An-Yeu Wu (DATE, 2024)

A 40nm 24.6TOPS/W Scalable EfficientDet Processor for Object Detection. - Yu-Chuan Chuang; Ming-Guang Lin; Chi-Tse Huang; Chieh-Fang Teng; Cheng-Yang Chang; Yi-Ta Chen; An-Yeu Andy Wu (ISCAS, 2024)

BFP-CIM: Runtime Energy-Accuracy Scalable Computing-in-Memory-Based DNN Accelerator Using Dynamic Block-Floating-Point Arithmetic. - Cheng-Yang Chang; Chi-Tse Huang; Yu-Chuan Chuang; Kuang-Chao Chou; An-Yeu Wu (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)