Modeling and analyzing of underwater acoustic channels with curvilinear boundaries in shallow ocean. - Rongkun Jiang; Shan Cao; Chengbo Xue; Lixing Tang (ICSPCC, 2017)

A two-stage variation-aware task mapping scheme for fault-tolerant multi-core Network-on-Chips. - Lei Zhang; Jianxun Yang; Chengbo Xue; Yue Ma; Shan Cao (ISCAS, 2017)

A Fast Modular Inversion FPGA Implementation over GF(2m) using Modified x2n Unit. - Jiakun Li; Zhe Li; Chengbo Xue; Jingqi Zhang; Wei Gao; Shan Cao (ISCAS, 2018)

A Reconfigurable Pipelined Architecture for Convolutional Neural Network Acceleration. - Chengbo Xue; Shan Cao; Rongkun Jiang; Hao Yang (ISCAS, 2018)

A Pre-RTL Simulator for Neural Networks. - Shan Cao; Zhenyi Bao; Chengbo Xue; Wei Deng; Shugong Xu; Shunqing Zhang (ISCAS, 2019)

SimuNN: A Pre-RTL Inference, Simulation and Evaluation Framework for Neural Networks. - Shan Cao; Wei Deng; Zhenyi Bao; Chengbo Xue; Shugong Xu; Shunqing Zhang (IEEE J. Emerg. Sel. Topics Circuits Syst., 2020)

DOA estimation based on sum-difference coarray with virtual array interpolation concept. - Yarong Ding; Shiwei Ren; Weijiang Wang; Chengbo Xue (EURASIP J. Adv. Signal Process., 2021)

Hardware Acceleration of MUSIC Algorithm for Sparse Arrays and Uniform Linear Arrays. - Zeying Li; Weijiang Wang; Rongkun Jiang; Shiwei Ren; Xiaohua Wang; Chengbo Xue (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Deep Learning-Aided Signal Detection for Two-Stage Index Modulated Universal Filtered Multi-Carrier Systems. - Rongkun Jiang; Zesong Fei; Shan Cao; Chengbo Xue; Ming Zeng 001; Qingqing Tang; Shiwei Ren (IEEE Trans. Cogn. Commun. Netw., 2022)

A Hardware Acceleration of Maximum Likelihood Estimation Algorithm With Alternating Projection on FPGA. - Zhuo Xuan; Shiwei Ren; Chengbo Xue; Guiyu Wang; Xiangnan Li (IEEE Trans. Very Large Scale Integr. Syst., 2024)