Chenggang Wu

Orcid: 0000-0003-1777-8110

Affiliations:
  • State Key Laboratory of Computer Architecture, Chinese Academy of Sciences, Huairou, Beijing, China


According to our database1, Chenggang Wu authored at least 33 papers between 2006 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
SpecWands: An Efficient Priority-Based Scheduler Against Speculation Contention Attacks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

Dancing With Wolves: An Intra-Process Isolation Technique With Privileged Hardware.
IEEE Trans. Dependable Secur. Comput., 2023

SpecBox: A Label-Based Transparent Speculation Scheme Against Transient Execution Attacks.
IEEE Trans. Dependable Secur. Comput., 2023

Khaos: The Impact of Inter-procedural Code Obfuscation on Binary Diffing Techniques.
Proceedings of the 21st ACM/IEEE International Symposium on Code Generation and Optimization, 2023

PANIC: PAN-assisted Intra-process Memory Isolation on ARM.
Proceedings of the 2023 ACM SIGSAC Conference on Computer and Communications Security, 2023

2022
Making Information Hiding Effective Again.
IEEE Trans. Dependable Secur. Comput., 2022

FuncFooler: A Practical Black-box Attack Against Learning-based Binary Code Similarity Detection Methods.
CoRR, 2022

Ferry: State-Aware Symbolic Execution for Exploring State-Dependent Program Paths.
Proceedings of the 31st USENIX Security Symposium, 2022

SoftTRR: Protect Page Tables against Rowhammer Attacks using Software-only Target Row Refresh.
Proceedings of the 2022 USENIX Annual Technical Conference, 2022

KOP-Fuzzer: A Key-Operation-based Fuzzer for Type Confusion Bugs in JavaScript Engines.
Proceedings of the 46th IEEE Annual Computers, Software, and Applications Conferenc, 2022

CETIS: Retrofitting Intel CET for Generic and Efficient Intra-process Memory Isolation.
Proceedings of the 2022 ACM SIGSAC Conference on Computer and Communications Security, 2022

2020
SEIMI: Efficient and Secure SMAP-Enabled Intra-process Memory Isolation.
Proceedings of the 2020 IEEE Symposium on Security and Privacy, 2020

2019
SafeHidden: An Efficient and Secure Information Hiding Technique Using Re-randomization.
Proceedings of the 28th USENIX Security Symposium, 2019

2018
Using Local Clocks to Reproduce Concurrency Bugs.
IEEE Trans. Software Eng., 2018

2017
ReRanz: A Light-Weight Virtual Machine to Mitigate Memory Disclosure Attacks.
Proceedings of the 13th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, 2017

SysMon: Monitoring Memory Behaviors via OS Approach.
Proceedings of the Advanced Parallel Processing Technologies, 2017

2016
Memos: A full hierarchy hybrid memory management framework.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

2015
FPS: A Fair-Progress Process Scheduling Policy on Shared-Memory Multiprocessors.
IEEE Trans. Parallel Distributed Syst., 2015

HSPT: Practical Implementation and Efficient Management of Embedded Shadow Page Tables for Cross-ISA System Virtual Machines.
Proceedings of the 11th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, 2015

ReCBuLC: Reproducing Concurrency Bugs Using Local Clocks.
Proceedings of the 37th IEEE/ACM International Conference on Software Engineering, 2015

2014
Dynamic I/O-Aware Scheduling for Batch-Mode Applications on Chip Multiprocessor Systems of Cluster Platforms.
J. Comput. Sci. Technol., 2014

Concurrency bug localization using shared memory access pairs.
Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2014

Localization of concurrency bugs using shared memory access pairs.
Proceedings of the ACM/IEEE International Conference on Automated Software Engineering, 2014

Dynamic and Adaptive Calling Context Encoding.
Proceedings of the 12th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2014

2013
Synchronization Identification through On-the-Fly Test.
Proceedings of the Euro-Par 2013 Parallel Processing, 2013

2012
On-the-fly structure splitting for heap objects.
ACM Trans. Archit. Code Optim., 2012

Providing fairness on shared-memory multiprocessors via process scheduling.
Proceedings of the ACM SIGMETRICS/PERFORMANCE Joint International Conference on Measurement and Modeling of Computer Systems, 2012

2011
Efficient and effective misaligned data access handling in a dynamic binary translation system.
ACM Trans. Archit. Code Optim., 2011

Dynamic register promotion of stack variables.
Proceedings of the CGO 2011, 2011

2010
On improving heap memory layout by dynamic pool allocation.
Proceedings of the CGO 2010, 2010

On mitigating memory bandwidth contention through bandwidth-aware scheduling.
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2009
An Evaluation of Misaligned Data Access Handling Mechanisms in Dynamic Binary Translation Systems.
Proceedings of the CGO 2009, 2009

2006
Library Function Disposing Approach in Binary Translation.
J. Comput. Res. Dev., 2006


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