A 400 μW Near-Threshold Feedback Class-C VCO with Auto Amplitude Control. - Chenggang Yan 002; Chen Hu (J. Circuits Syst. Comput., 2018)

A low power wide tuning range two stage ring VCO with frequency enhancing. - Chenggang Yan 002; Jianhui Wu 001; Chen Hu; Xincun Ji (IEICE Electron. Express, 2019)

A digital-mixing-based method for timing skew estimation in time-interleaved ADCs. - Xin Li 099; Desheng Ding; Chenggang Yan 002; Jianhui Wu 001 (Microelectron. J., 2019)

Active Noise Shaping SAR ADC Based on ISDM with the 5MHz Bandwidth. - Bo Gao; Xin Li 099; Chenggang Yan 002; Jianhui Wu 001 (ISCAS, 2020)

A Low-Spur MASH Delta-Sigma Modulator With an Adaptive Length Extension Technique. - Xin Ding 003; Chenggang Yan 002; Xin Li 099; Jianhui Wu 001 (IEEE Trans. Circuits Syst., 2020)

A Low Phase Noise Open Loop Fractional-N Frequency Synthesizer With Injection Locking Digital Phase Modulator. - Chenggang Yan 002; Jianhui Wu 001; Jie Sun 020; Jin Jin; Chen Hu (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A Dynamic Highly Reliable SRAM-Based PUF Retaining Memory Function. - Hu Zhang; Chenghua Wang; Chenggang Yan 002; Yijun Cui; Chongyan Gu; Máire O'Neill; Weiqiang Liu 001 (ISCAS, 2021)

Design of An Approximate FFT Processor Based on Approximate Complex Multipliers. - Jinhe Du; Ke Chen 018; Peipei Yin; Chenggang Yan 002; Weiqiang Liu 001 (ISVLSI, 2021)

Background Calibration for Bit Weights in Pipelined ADCs Using Adaptive Dither Windows. - Jie Sun 020; Xin Ding 003; Chenggang Yan 002; Weiqiang Liu 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

An Efficient High SFDR PDDS Using High-Pass-Shaped Phase Dithering. - Chenggang Yan 002; Jie Sun 020; Weiqiang Liu 001 (IEEE Trans. Very Large Scale Integr. Syst., 2021)

An Energy-Efficient Approximate Floating-Point Multipliers for Wireless Communications. - Jipeng Ge; Chenggang Yan 002; Xuan Zhao; Ke Chen 018; Bi Wu; Weiqiang Liu 001 (APCCAS, 2022)

Design of Approximate Floating-point FFT with Mantissa Bit-width Adjustment Algorithm. - Xuan Zhao; Chenggang Yan 002; Chenghua Wang; Weiqiang Liu 001 (APCCAS, 2022)

An Energy-efficient and High-precision Approximate MAC with Distributed Arithmetic Circuits. - Ziying Cui; Ke Chen 018; Bi Wu; Chenggang Yan 002; Weiqiang Liu 001 (ACM Great Lakes Symposium on VLSI, 2022)

Data Stream Oriented Fine-grained Sparse CNN Accelerator with Efficient Unstructured Pruning Strategy. - Tianyang Yu; Bi Wu; Ke Chen 018; Chenggang Yan 002; Weiqiang Liu 001 (ACM Great Lakes Symposium on VLSI, 2022)

Energy-efficient Oriented Approximate Quantization Scheme for Fine-Grained Sparse Neural Network Acceleration. - Tianyang Yu; Bi Wu; Ke Chen 018; Chenggang Yan 002; Weiqiang Liu 001 (ICCD, 2022)

GBC: An Energy-Efficient LSTM Accelerator With Gating Units Level Balanced Compression Strategy. - Bi Wu; Zhengkuan Wang; Ke Chen 018; Chenggang Yan 002; Weiqiang Liu 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

High Performance and Hardware-Efficient Approximate BPF Decoder for Polar codes. - Yuxuan Cui; Chenggang Yan 002; Weiqiang Liu 001 (ISCAS, 2023)

Hardware-Efficient Accurate and Approximate FPGA Multipliers for Error-Tolerant Applications. - Haonan Wang; Ke Chen 018; Chenggang Yan 002; Bi Wu; Weiqiang Liu 001 (MWSCAS, 2023)

A High Accuracy and Hardware Efficient Adaptive Filter Design with Approximate Computing. - Wenzhuo Xie; Chenggang Yan 002; Hanghang Wang; Ke Chen 018; Bi Wu; Chenghua Wang; Weiqiang Liu 001 (MWSCAS, 2023)

MLiM: High-Performance Magnetic Logic in-Memory Scheme With Unipolar Switching SOT-MRAM. - Bi Wu; Haonan Zhu; Ke Chen 018; Chenggang Yan 002; Weiqiang Liu 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Hardware Efficient Successive-Cancellation Polar Decoders Using Approximate Computing. - Chenggang Yan 002; Yuxuan Cui; Ke Chen 018; Bi Wu; Weiqiang Liu 001 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)

Design of High Hardware Efficiency Approximate Floating-Point FFT Processor. - Chenggang Yan 002; Xuan Zhao; Tingting Zhang; Jipeng Ge; Chenghua Wang; Weiqiang Liu 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A Time Efficient Comprehensive Model of Approximate Multipliers for Design Space Exploration. - Ziying Cui; Ke Chen 018; Bi Wu; Chenggang Yan 002; Yu Gong; Weiqiang Liu 001 (ARITH, 2024)

Toward Efficient Retraining: A Large-Scale Approximate Neural Network Framework With Cross-Layer Optimization. - Tianyang Yu; Bi Wu; Ke Chen 018; Chenggang Yan 002; Weiqiang Liu 001 (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A Potential Enabler for High-Performance In-Memory Multi-Bit Arithmetic Schemes With Unipolar Switching SOT-MRAM. - Haonan Zhu; Bi Wu; Tianyang Yu; Ke Chen 018; Chenggang Yan 002; Weiqiang Liu 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)