An ECG Automatic Detection System with Baseline Drift Removal Based on SG Filter. - Jiangbo Wei; Chenghao Zhang 004; Jiaji Ma 001; Zhihang Li; Maliang Liu (ASICON, 2021)

A 12-bit 1.25 GS/s RF sampling pipelined ADC using a bandwidth-expanded residue amplifier with bias-free gain-boost technique. - Chenghao Zhang 004; Jiangbo Wei; Yihang Yang; Maliang Liu (Microelectron. J., 2022)

A 11-Bit 1-GS/s 14.9mW Hybrid Voltage-Time Pipelined ADC With Gain Error Calibration. - Jiangbo Wei; Chenghao Zhang 004; Maliang Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Reconfigurable 8-to-10-bit 20-to-5-GS/s time-interleaved time-domain ADC. - Jiangbo Wei; Chenghao Zhang 004; Xinyu Wang; Yuan Chang; Maliang Liu (Microelectron. J., 2023)

A 0.004-mm2 3.65-mW 7-Bit 2-GS/s Single-Channel GRO-Based Time-Domain ADC Incorporating Dead-Zone Elimination and On-Chip Folding-Offset Calibration in 28-nm CMOS. - Chenghao Zhang 004; Jiangbo Wei; Yong Chen 005; Maliang Liu; Yintang Yang (IEEE J. Solid State Circuits, 2023)

A 6.86mW 1.5 GS/s 9 b Pipelined SAR ADC with TDC-Assisted Residue Quantization. - Chenghao Zhang 004; Maliang Liu; Yuan Chang; Yihang Yang; Jinhai Xiao; Yintang Yang; Yuanjin Zheng (ISCAS, 2025)

An 8-Bit 4-GS/s Single-Channel Two-Step ADC Featuring Non-Symmetrical Pipeline Timing and Hybrid-Loop Amplifier. - Chenghao Zhang 004; Maliang Liu; Yuan Chang; Yihang Yang; Jinhai Xiao; Yintang Yang; Yuanjin Zheng; Yong Chen 005 (IEEE Trans. Very Large Scale Integr. Syst., 2025)