Radiation-hardened 14T SRAM cell by polar design for space applications. - Licai Hao; Bin Qiang; Chenghu Dai; Chunyu Peng; Wenjuan Lu; Zhiting Lin; Li Liu 004; Qiang Zhao 007; Xiulong Wu; Fei Sun (IEICE Electron. Express, 2023)

Bit-line leakage current tracking and self-compensation circuit for SRAM reliability design. - Chenghu Dai; Yuanyuan Du; Qi Shi; Ruixuan Wang; Hao Zheng; Wenjuan Lu; Chunyu Peng; Licai Hao; Zhiting Lin; Xiulong Wu (Microelectron. J., 2023)

Design of radiation-hardened memory cell by polar design for space applications. - Licai Hao; Li Liu 004; Qi Shi; Bin Qiang; Zhengya Li; Nianlong Liu; Chenghu Dai; Qiang Zhao 007; Chunyu Peng; Wenjuan Lu; Zhiting Lin; Xiulong Wu (Microelectron. J., 2023)

A 9T-SRAM based computing-in-memory with redundant unit and digital operation for boolean logic and MAC. - Xin Li 099; Mengya Gao; Zihua Ren; Kefeng Yu; Wenjuan Lu; Chenghu Dai; Wei Hu; Chunyu Peng; Xiulong Wu (Microelectron. J., 2024)

Corrigendum to "A 9T-SRAM based computing-in-memory with redundant unit and digital operation for boolean logic and MAC" [145, March 2024, 106124. - Xin Li 099; Mengya Gao; Zihua Ren; Kefeng Yu; Wenjuan Lu; Chenghu Dai; Wei Hu; Chunyu Peng; Xiulong Wu (Microelectron. J., 2024)

A 28-nm 9T SRAM-based CIM macro with capacitance weighting module and redundant array-assisted ADC. - Zhiting Lin; Runru Yu; Da Huo; Qingchuan Zhu; Miao Long; Yongqi Qin; Yanchun Liu; Lintao Chen; Simin Wang; Ting Wang; Yousheng Xing; Zeshi Wen; et al. (Microelectron. J., 2024)

Cross-coupled 4T2R multi-logic in-memory computing circuit design. - Zhiting Lin; Changxin Yue; Ke Li; Qiushi Feng; Siyan Li; Yue Zhao; Yuanyang Wang; Jiaqi Chen; Wenjuan Lu; Chunyu Peng; Qiang Zhao 007; Chenghu Dai; et al. (Microelectron. J., 2024)

High energy efficient and configurable CIM macro for image processing. - Chunyu Peng; Shengyuan Yan; Huayi Ding; Yana Wang; Wenjuan Lu; Chenghu Dai; Xin Li 099; Wei Hu; Xiulong Wu (Microelectron. J., 2024)

A CFMB STT-MRAM-Based Computing-in-Memory Proposal With Cascade Computing Unit for Edge AI Devices. - Yongliang Zhou; Zixuan Zhou; Yiming Wei; Zhen Yang; Xiao Lin; Chenghu Dai; Licai Hao; Chunyu Peng; Hao Cai 001; Xiulong Wu (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A 9T-SRAM in-memory computing macro for Boolean logic and multiply-and-accumulate operations. - Chenghu Dai; Zihua Ren; Lijun Guan; Haitao Liu; Mengya Gao; Wenjuan Lu; Zhiyong Pang; Chunyu Peng; Xiulong Wu (Microelectron. J., 2024)

Flip Point Offset-Compensation Sense Amplifier With Sensing-Margin-Enhancement for Dynamic Random-Access Memory. - Li Liu 004; Dele Tai; Bin Qiang; Lijun Guan; Chunyu Peng; Chenghu Dai; Licai Hao; Wenjuan Lu; Zhiting Lin; Qiang Zhao 007; Xiulong Wu (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch Based on Polarity Design and Source-Isolation Technologies. - Licai Hao; Xinyi Zhang; Chenghu Dai; Qiang Zhao 007; Wenjuan Lu; Chunyu Peng; Yongliang Zhou; Zhiting Lin; Xiulong Wu (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Low-Cost and Highly Robust Quadruple Node Upset Tolerant Latch Design. - Licai Hao; Yaling Wang; Yunlong Liu; Shiyu Zhao; Xinyi Zhang; Yang Li; Wenjuan Lu; Chunyu Peng; Qiang Zhao 007; Yongliang Zhou; Chenghu Dai; Zhiting Lin; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2024)

High-Performance Latch Designs of Double-Node-Upset Self-Recovery and Triple-Node-Upset Tolerance for Aerospace Applications. - Chunyu Peng; Lang Tian; Licai Hao; Qiang Zhao 007; Chenghu Dai; Zhiting Lin; Xiulong Wu (IEEE Trans. Aerosp. Electron. Syst., 2024)

TSCIM: A 28nm Transposed Stochastic CIM Macro for On-Chip Training and Inference. - Yu Liu 030; Yang Lou; Kangkang Mao; Xin Li 099; Chenghu Dai; Xiulong Wu; Zhiting Lin (ISCAS, 2025)

A PVT-insensitive 7T SRAM CIM macro for multibit multiplication with dynamic matching quantization circuits. - Chenghu Dai; Jianhao Zhang; Ruixuan Wang; Junbo Chen; Wei Hu; Licai Hao; Wenjuan Lu; Zhiting Lin; Chunyu Peng; Xiulong Wu (Microelectron. J., 2025)

Low-power 12T TFET-MOSFET hybrid SRAM bitcell and hybrid 8T SRAM array based on multiplexing strategy. - Wei Hu; Qizhong Zhang; Chenghu Dai; Chunyu Peng; Wenjuan Lu; Xiulong Wu (Microelectron. J., 2025)

Hybrid MOSFET-TFET 11T SRAM cell with high write speed and free half-selected disturbance. - Wenjuan Lu; Chuang Wang; Wei Hu; Chenghu Dai; Chunyu Peng; Zhiting Lin; Xiulong Wu (Microelectron. J., 2025)

Real-time bit-line leakage balance circuit with four-input low-offset SA considering threshold voltage for SRAM stability design. - Chunyu Peng; Wei Hu; Hao Zheng; Wenjuan Lu; Chenghu Dai; Xiulong Wu; Zhiting Lin; Junning Chen (Int. J. Circuit Theory Appl., 2025)

A Low-Cost and Triple-Node-Upset Self-Recoverable Latch Design With Low Soft Error Rate. - Licai Hao; Lang Tian; Hao Wang; Shiyu Zhao; Qiang Zhao 007; Chunyu Peng; Chenghu Dai; Zhi-Ting Lin; Xiulong Wu (IEEE Trans. Very Large Scale Integr. Syst., 2025)

High-Reliability and High-Throughput CIM 10T-SRAM for Multiplication and Accumulation Operations With 274.3 GOPS and 200-237.5 TOPS/W. - Wenjuan Lu; Lubin Xiang; Ling Wang; Chunyu Peng; Chenghu Dai; Zhiting Lin; Xiulong Wu (IEEE Trans. Very Large Scale Integr. Syst., 2025)

8T-SRAM Computing-in-Memory Macro with Bitline Leakage Compensation. - Chunyu Peng; Junbo Chen; Mengyi Zhao; Wenjuan Lu; Zhiting Lin; Licai Hao; Xin Li 099; Chenghu Dai; Xiulong Wu (Circuits Syst. Signal Process., 2025)

A 28-nm 9T1C SRAM-Based CIM Macro With Hierarchical Capacitance Weighting and Two-Step Capacitive Comparison ADCs for CNNs. - Zhiting Lin; Runru Yu; Yunhao Li; Miao Long; Yu Liu 030; Jianxing Zhou; Da Huo; Qingchuan Zhu; Yue Zhao; Lintao Chen; Chunyu Peng; Qiang Zhao 007; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A 28-nm Cascode Current Mirror-Based Inconsistency-Free Charging-and-Discharging SRAM-CIM Macro for High-Efficient Convolutional Neural Networks. - Chunyu Peng; Jiating Guo; Shengyuan Yan; Yiming Wei; Xiaohang Chen; Wenjuan Lu; Chenghu Dai; Zhiting Lin; Xiulong Wu (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A 28 nm Dual-Mode SRAM-CIM Macro With Local Computing Cell for CNNs and Grayscale Edge Detection. - Chunyu Peng; Xiaohang Chen; Mengya Gao; Jiating Guo; Lijun Guan; Chenghu Dai; Zhiting Lin; Xiulong Wu (IEEE Trans. Very Large Scale Integr. Syst., 2025)