Snap-3D: A Constrained Placement-Driven Physical Design Methodology for Face-to-Face-Bonded 3D ICs. - Pruek Vanna-Iampikul; Chengjia Shao; Yi-Chen Lu; Sai Pentapati; Sung Kyu Lim (ISPD, 2021)

Snap-3D: A Constrained Placement-Driven Physical Design Methodology for High Performance 3-D ICs. - Pruek Vanna-Iampikul; Chengjia Shao; Yi-Chen Lu; Sai Pentapati; Yun Heo; Jae-Seung Choi; Sung Kyu Lim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

A Novel Resynchronization Circuit to Enable High-Accuracy PTP Timestamping. - Chengjia Shao; Zhen Xu; Harihara S. Ranganathan (IEEE Trans. Instrum. Meas., 2024)