32.2 A 14nm Analog Sampling Fractional-N PLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 80fs Integrated Jitter and 93fs at Near-Integer Channels. - Wanghua Wu; Chih-Wei Yao; Chengkai Guo; Pei-Yuan Chiang; Pak-Kim Lau; Lei Chen; Sang Won Son; Thomas Byunghak Cho (ISSCC, 2021)

A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO. - Wanghua Wu; Chih-Wei Yao; Chengkai Guo; Pei-Yuan Chiang; Lei Chen; Pak-Kim Lau; Zhanjun Bai; Sang Won Son; Thomas Byunghak Cho (IEEE J. Solid State Circuits, 2021)

A 16-Channel, 28/39GHz Dual-Polarized 5G FR2 Phased-Array Transceiver IC with a Quad-Stream IF Transceiver Supporting Non-Contiguous Carrier Aggregation up to 1.6GHz BW. - Ashutosh Verma; Venumadhav Bhagavatula; Amitoj Singh; Wanghua Wu; Hariharan Nagarajan; Pak-Kim Lau; Xiaohua Yu; Omar Elsayed; Ajaypat Jain; Anirban Sarkar 002; Fan Zhang; Che-Chun Kuo; et al. (ISSCC, 2022)