A Memory Optimized Architecture for Multi-Field Packet Classification (Brief Announcement). - Chenglong Li 007; Tao Li 008; Junnan Li 002; Hui Yang; Baosheng Wang (SPAA, 2019)

Update Latency Optimization of Packet Classification for SDN Switch on FPGA. - Chenglong Li 007; Tao Li 008; Junnan Li 002; Zilin Shi; Baosheng Wang (FCCM, 2020)

MsBV: A Memory Compression Scheme for Bit-Vector-Based Classification Lookup Tables. - Zilin Shi; Hui Yang; Junnan Li 002; Chenglong Li 007; Tao Li 008; Baosheng Wang (IEEE Access, 2020)

CAMES: enabling centralized automotive embedded systems with time-sensitive network. - Xiangrui Yang 002; Chenglong Li 007; Ling Yang 008; Chuhao Han; Tao Li 008; Zhigang Sun (SIGCOMM Posters and Demos, 2021)

Poster Abstract: A Network-on-Chip Router Architecture for Industrial Internet-of-Thing Gateways. - Chenglong Li 007; Cunlu Li; Wenwen Fu; Tao Li 008; Baosheng Wang (IPSN, 2023)

DRA: Ultra-Low Latency Network I/O for TSN Embedded End-Systems. - Chenglong Li 007; Tao Li 008; Junnan Li 002; Wenwen Fu; Baosheng Wang (IWQoS, 2023)

Octopus: A Heterogeneous In-network Computing Accelerator Enabling Deep Learning for network. - Dong Wen 004; Tao Li 008; Chenglong Li 007; Pengye Xia; Hui Yang; Zhigang Sun (CoRR, 2023)

A Deterministic Embedded End-System Tightly Coupled With TSN Schedule. - Chenglong Li 007; Zonghui Li; Tao Li 008; Cunlu Li; Baosheng Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Inference-to-complete: A High-performance and Programmable Data-plane Co-processor for Neural-network-driven Traffic Analysis. - Dong Wen 004; Zhongpei Liu; Tong Yang 003; Tao Li 008; Tianyun Li; Chenglong Li 007; Jie Li; Zhigang Sun (CoRR, 2024)