A 47K Noise Temperature CMOS S-band LNA for Cryogenic Applications. - Yi Xie; Chenglong Liang; Bingjun Tang; Lingyun Liu; Li Geng (ICTA, 2021)

A 0.025% DC Current Mismatch Charge Pump for PLL Applications. - Shengyu Liang; Youze Xin; Chenglong Liang; Bin Zhang; Yanlong Zhang; Xiaoli Wang; Li Geng (MWSCAS, 2021)

A Cap-Less High PSR and Low Output Noise Low-Dropout Regulator for Cryogenic Applications. - Lingyun Liu; Chenglong Liang; Zhuoqi Guo; Zhongming Xue; Li Geng (ICTA, 2022)

A 12.9-to-24 GHz Dual-Mode Multi-Coil VCO Achieving 199.2 dBc/Hz Peak FoMT in 65-nm CMOS. - Ya Zhao; Chao Fan; Yuanxing Peng; Chenglong Liang; Jun Yin 001; Pui-In Mak; Li Geng (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Design of CMOS Integrated Circulator Based on Sequentially Switched Delay Lines With Body-Floating and Clock Boosting Techniques. - Bingjun Tang; Yuanrui Li; Chenglong Liang; Zhongming Xue; Zhuoqi Guo; Li Geng (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 5.5-7.9 GHz Double Quadrature Cryo-CMOS Receiver Featuring a Wideband Noise Matching LNA for Quantum Applications. - Zixun Gao; Chenglong Liang; Suyuan Gan; Bingjun Tang; Xingguo Dong; Ya Zhao; Youze Xin; Li Geng (ISCAS, 2025)