A 16K Current-Based 8T SRAM Compute-In-Memory Macro with Decoupled Read/Write and 1-5bit Column ADC. - Chengshuo Yu; Taegeun Yoo; Tony Tae-Hyoung Kim; Kevin Tshun Chuan Chai; Bongjin Kim (CICC, 2020)

Design of Current-Mode 8T SRAM Compute-In-Memory Macro for Processing Neural Networks. - Taegeun Yoo; Tony Tae-Hyoung Kim; Bongjin Kim; Chengshuo Yu; Kevin Chai Tshun Chuan (ISOCC, 2020)

A 32x32 Time-Domain Wavefront Computing Accelerator for Path Planning and Scientific Simulations. - Chengshuo Yu; Yuqi Su; Jaeho Lee; Kevin T. C. Chai; Bongjin Kim (CICC, 2021)

A Zero-Skipping Reconfigurable SRAM In-Memory Computing Macro with Binary-Searching ADC. - Chengshuo Yu; Kevin Tshun Chuan Chai; Tony Tae-Hyoung Kim; Bongjin Kim (ESSDERC, 2021)

A Logic-Compatible eDRAM Compute-In-Memory With Embedded ADCs for Processing Neural Networks. - Chengshuo Yu; Taegeun Yoo; Hyunjoon Kim; Tony Tae-Hyoung Kim; Kevin Chai Tshun Chuan; Bongjin Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A Scalable Bit-Serial Computing Hardware Accelerator for Solving 2D/3D Partial Differential Equations Using Finite Difference Method. - Junjie Mu; Chengshuo Yu; Tony Tae-Hyoung Kim; Bongjin Kim (ESSCIRC, 2022)

An Overview of Processing-in-Memory Circuits for Artificial Intelligence and Machine Learning. - Donghyuk Kim; Chengshuo Yu; Shanshan Xie; Yuzong Chen 001; Joo-Young Kim 001; Bongjin Kim; Jaydeep P. Kulkarni; Tony Tae-Hyoung Kim (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

A 65-nm 8T SRAM Compute-in-Memory Macro With Column ADCs for Processing Neural Networks. - Chengshuo Yu; Taegeun Yoo; Kevin Tshun Chuan Chai; Tony Tae-Hyoung Kim; Bongjin Kim (IEEE J. Solid State Circuits, 2022)

A Continuous-Time Ising Machine using Coupled Inverter Chains Featuring Fully-Parallel One-Shot Spin Updates. - Chengshuo Yu; Junjie Mu; Kevin Tshun-Chuan Chai; Tony T. Kim; Bongjin Kim (CICC, 2023)

282-to-607 TOPS/W, 7T-SRAM Based CiM with Reconfigurable Column SAR ADC for Neural Network Processing. - Qibang Zang; Wang Ling Goh; Lu Lu 013; Chengshuo Yu; Junjie Mu; Tony Tae-Hyoung Kim; Bongjin Kim; Dongrui Li; Anh Tuan Do (ISCAS, 2023)

A Bit-Serial Computing Accelerator for Solving Coupled Partial Differential Equations. - Junjie Mu; Chengshuo Yu; Tony Tae-Hyoung Kim; Bongjin Kim (VLSI Technology and Circuits, 2023)

A Time-Domain Wavefront Computing Accelerator With a 32 × 32 Reconfigurable PE Array. - Chengshuo Yu; Junjie Mu; Yuqi Su; Kevin Tshun Chuan Chai; Tony Tae-Hyoung Kim; Bongjin Kim (IEEE J. Solid State Circuits, 2023)

A 1-16b Reconfigurable 80Kb 7T SRAM-Based Digital Near-Memory Computing Macro for Processing Neural Networks. - Hyunjoon Kim; Junjie Mu; Chengshuo Yu; Tony Tae-Hyoung Kim; Bongjin Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

CTLE-Ising: A Continuous-Time Latch-Based Ising Machine Featuring One-Shot Fully Parallel Spin Updates and Equalization of Spin States. - Jooyoung Bae; Wonsik Oh; Jahyun Koo 003; Chengshuo Yu; Bongjin Kim (IEEE J. Solid State Circuits, 2024)

A Scalable and Reconfigurable Bit-Serial Compute-Near-Memory Hardware Accelerator for Solving 2-D/3-D Partial Differential Equations. - Junjie Mu; Chengshuo Yu; Tony Tae-Hyoung Kim; Bongjin Kim (IEEE J. Solid State Circuits, 2024)

A Dual 7T SRAM-Based Zero-Skipping Compute- In-Memory Macro With 1-6b Binary Searching ADCs for Processing Quantized Neural Networks. - Chengshuo Yu; Haoge Jiang; Junjie Mu; Kevin Tshun Chuan Chai; Tony Tae-Hyoung Kim; Bongjin Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A Refresh-Reduction Digital eDRAM CIM Macro using Asymmetric Error Tolerance Scheme. - Yue Cao; Yuanyuan Han; Keji Zhou; Chengshuo Yu; Tianci Cai; Jianguo Yang (ISCAS, 2025)

A High-Density RRAM-Based Ising Machine with Analog In-Memory Operation for Solving Combinatorial Optimization Problems. - Jingxin Deng; Keji Zhou; Honghu Yang; Chengshuo Yu; Jianguo Yang (ISCAS, 2025)

A High Performance Dual-Wordline RRAM Macro with Replica Bitline Delay Control Circuit. - Honghu Yang; Yongkang Han; Tianci Cai; Chengshuo Yu; Keji Zhou; Jianguo Yang (ISCAS, 2025)

Enhancing All-to-All RRAM Ising Machines With Randomized Granular Update Strategies for Solving Combinatorial Optimization Problems. - Yixuan Liu; Qiqiao Wu; Honghu Yang; Chengshuo Yu; Keji Zhou; Yu Jiang; Haijun Jiang; Hailan Yi; Xiaoyong Xue; Jianguo Yang; Xiaoyang Zeng (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)