AutoShrink: A Topology-Aware NAS for Discovering Efficient Neural Architecture. - Tunhou Zhang; Hsin-Pai Cheng; Zhenwen Li; Feng Yan 001; Chengyu Huang 001; Hai Helen Li; Yiran Chen 001 (AAAI, 2020)

A 16-Bit 4.0-GS/s Calibration-Free 65nm DAC with >70dBc SFDR and <-80dBc IM3 up to 1GHz Using Constant-Activity Element Switching. - Chengyu Huang 001; Yushen Fu; Zekun Yang; Yang Liu; Nan Sun 001; Xueqing Li 002; Huazhong Yang (ESSCIRC, 2021)

Dynamic Switching Sequence to Compensate the Integral Nonlinearity in Current-Steering DACs. - Yang Liu; Yushen Fu; Chengyu Huang 001; Huazhong Yang; Xueqing Li 002 (ISCAS, 2021)

A 6.0-GS/s Time-Interleaved DAC Using an Asymmetric Current-Tree Summation Network and Differential Clock Timing Calibration. - Yushen Fu; Chengyu Huang 001; Limeng Sun; Weiguang Meng; Xueqing Li 002; Huazhong Yang (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A 16-Bit 4.0-GS/s Calibration-Free 65 nm DAC Achieving >70 dBc SFDR and < -80 dBc IM3 Up to 1 GHz With Enhanced Constant-Switching-Activity Data-Weighted-Averaging. - Yushen Fu; Chengyu Huang 001; Longqiang Lai; Nan Sun 001; Xueqing Li 002; Huazhong Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 16-bit 10-GS/s Calibration-Free DAC Achieving <-77dBc IM3 up to 4.95GHz in 28nm CMOS. - Chengyu Huang 001; Kezhuo Ma; Sihao Chen; Jiaxuan Fan; Nan Sun 001; Huazhong Yang; Xueqing Li 002 (CICC, 2024)

A 28-nm 8-Bit 16-GS/ DAC With >60 dBc/>40 dBc SFDR Up To 2.3 GHz/5.4 GHz Using 4-Channel NRZ-Output-Overlapped Time-Interleaving. - Sihao Chen; Chengyu Huang 001; Limeng Sun; Yang Liu; Wenjun Tang; Jiaxuan Fan; Nan Sun 001; Yong Chen 005; Huazhong Yang; Xueqing Li 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2025)