System-level optimization and benchmarking of graphene PN junction logic system based on empirical CPI model. - Chenyun Pan; Azad Naeemi (ICICDT, 2012)

Device- and system-level performance modeling for graphene P-N junction logic. - Chenyun Pan; Azad Naeemi (ISQED, 2012)

System-level optimization and benchmarking for InAs nanowire based gate-all-around tunneling FETs. - Chenyun Pan; Ahmet Ceyhan; Azad Naeemi (ISQED, 2013)

BEOL Scaling Limits and Next Generation Technology Prospects. - Azad Naeemi; Ahmet Ceyhan; Vachan Kumar; Chenyun Pan; Rouhollah M. Iraei; Shaloo Rakheja (DAC, 2014)

An analytical approach to system-level variation analysis and optimization for multi-core processor. - Chenyun Pan; Saibal Mukhopadhyay; Azad Naeemi (ISQED, 2014)

Technology/circuit co-optimization and benchmarking for graphene interconnects at Sub-10nm technology node. - Chenyun Pan; Praveen Raghavan; Francky Catthoor; Zsolt Tokei; Azad Naeemi (ISQED, 2015)

A Fast System-Level Design Methodology for Heterogeneous Multi-Core Processors Using Emerging Technologies. - Chenyun Pan; Azad Naeemi (IEEE J. Emerg. Sel. Topics Circuits Syst., 2015)

Device/system performance modeling of stacked lateral NWFET logic. - Victor Huang; Chenyun Pan; Dmitry Yakimets; Praveen Raghavan; Azad Naeemi (ISQED, 2016)

Performance modeling and optimization for on-chip interconnects in 3D memory arrays. - Javaneh Mohseni; Chenyun Pan; Azad Naeemi (ISQED, 2016)

Impact of interconnect variability on circuit performance in advanced technology nodes. - Divya Prasad; Chenyun Pan; Azad Naeemi (ISQED, 2016)

A Proposal for Energy-Efficient Cellular Neural Network based on Spintronic Devices. - Chenyun Pan; Azad Naeemi (CoRR, 2016)

Beyond-CMOS non-Boolean logic benchmarking: Insights and future directions. - Chenyun Pan; Azad Naeemi (DATE, 2017)

Beyond-CMOS Device Benchmarking for Boolean and Non-Boolean Logic Applications. - Chenyun Pan; Azad Naeemi (CoRR, 2017)

Generic system-level modeling and optimization for beyond CMOS device applications. - Victor Huang; Chenyun Pan; Azad Naeemi (ISQED, 2018)

A Mixed Signal Architecture for Convolutional Neural Networks. - Qiuwen Lou; Chenyun Pan; John McGuinness; András Horváth; Azad Naeemi; Michael T. Niemier; Xiaobo Sharon Hu (ACM J. Emerg. Technol. Comput. Syst., 2019)

Fast Linear Programming Optimization Using Crossbar-Based Analog Accelerator. - Liuting Shang; Muhammad Adil; Ramtin Madani; Chenyun Pan (ISVLSI, 2020)

Technology/Memory Co-Design and Co-Optimization Using E-Tree Interconnect. - Zhenlin Pei; Mahta Mayahinia; Hsiao-Hsuan Liu; Mehdi B. Tahoori; Francky Catthoor; Zsolt Tokei; Chenyun Pan (ACM Great Lakes Symposium on VLSI, 2023)

QPUF: Quantum Physical Unclonable Functions for Security-by-Design of Industrial Internet-of-Things. - Venkata K. V. V. Bathalapalli; Saraju P. Mohanty; Chenyun Pan; Elias Kougianos (iSES, 2023)

Emerging Interconnect Exploration for SRAM Application Using Nonconventional H-Tree and Center-Pin Access. - Zhenlin Pei; Mahta Mayahinia; Hsiao-Hsuan Liu; Mehdi B. Tahoori; Shairfe Muhammad Salahuddin; Francky Catthoor; Zsolt Tokei; Chenyun Pan (ISQED, 2023)

A Technology/Circuit Co-design Framework for Emerging Reconfigurable Devices. - Sheng Lu; Zhenlin Pei; Liuting Shang; Sungyong Jung; Chenyun Pan (MWSCAS, 2023)

Novel Fence Generation Methods for Accelerating Reconfigurable Exact Synthesis. - Liuting Shang; Sheng Lu; Sungyong Jung; Chenyun Pan (MWSCAS, 2023)

A statistical approach for neural network pruning with application to internet of things. - Chengchen Mao; Qilian Liang; Chenyun Pan; Ioannis D. Schizas (EURASIP J. Wirel. Commun. Netw., 2023)

Towards Area Efficient Logic Circuit: Exploring Potential of Reconfigurable Gate by Generic Exact Synthesis. - Liuting Shang; Azad Naeemi; Chenyun Pan (IEEE Open J. Comput. Soc., 2023)

Deep learning in physical layer communications: Evolution and prospects in 5G and 6G networks. - Chengchen Mao; Zongwen Mu; Qilian Liang; Ioannis D. Schizas; Chenyun Pan (IET Commun., 2023)

Emerging Reconfigurable Logic Device Based FPGA Design and Optimization. - Sheng Lu; Liuting Shang; Sungyong Jung; Chenyun Pan (ISQED, 2024)

A Novel Delay-Aware Packing Algorithm for FPGA Architecture Using RFET. - Sheng Lu; Liuting Shang; Sungyong Jung; Yichen Zhang 005; Chenyun Pan (MWSCAS, 2024)

A Low-Noise, Low-Offset CMOS Readout IC for Amperometric Biosensors. - Manu Chilukuri; Shanthala Lakshminarayana; Hyusim Park; Chenyun Pan; Hoon-Ju Chung; Sungyong Jung (IEEE Access, 2024)

Ultra-Scaled E-Tree-Based SRAM Design and Optimization With Interconnect Focus. - Zhenlin Pei; Hsiao-Hsuan Liu; Mahta Mayahinia; Mehdi B. Tahoori; Francky Catthoor; Zsolt Tokei; Dawit Burusie Abdi; James Myers; Chenyun Pan (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Dynamic Segmented Bus for Energy-Efficient Last-Level Cache in Advanced Interconnect-Dominant Nodes. - Mahta Mayahinia; Tommaso Marinelli; Zhenlin Pei; Hsiao-Hsuan Liu; Chenyun Pan; Zsolt Tokei; Francky Catthoor; Mehdi B. Tahoori (IEEE Embed. Syst. Lett., 2024)

Future Design Direction for SRAM Data Array: Hierarchical Subarray With Active Interconnect. - Hsiao-Hsuan Liu; Carlo Gilardi; Shairfe Muhammad Salahuddin; Zhenlin Pei; Pieter Schuddinck; Yang Xiang; Pieter Weckx; Geert Hellings; Marie Garcia Bardon; Julien Ryckaert; Chenyun Pan; Subhasish Mitra; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

QPUF 3.0: Sustainable Cybersecurity of Smart Grid through Security-By-Design based on Quantum-PUF and Quantum Key Distribution. - Venkata Karthik Vishnu Vardhan Bathalapalli; Saraju P. Mohanty; Chenyun Pan; Elias Kougianos (ACM Great Lakes Symposium on VLSI, 2025)

Graphene-Based FPGA Design and Optimization at the 7nm FinFET Technology Node. - Sheng Lu; Zhenlin Pei; Liuting Shang; Sungyong Jung; Qilian Liang; Chenyun Pan (ISQED, 2025)

QPUF 2.0: Exploring Quantum Physical Unclonable Functions for Security-by-Design of Energy Cyber-Physical Systems. - Venkata K. V. V. Bathalapalli; Saraju P. Mohanty; Chenyun Pan; Elias Kougianos (WoWMoM, 2025)