Subharmonically pumped CMOS frequency conversion (up and down) circuits for 2-GHz WCDMA direct-conversion transceiver. - Kwang-Jin Koh; Mun-Yang Park; Cheon-Soo Kim; Hyun-Kyu Yu (IEEE J. Solid State Circuits, 2004)

A 230ns settling time type-I PLL with 0.96mW TDC power and simple TV calculation algorithm. - Ja-Yol Lee; Mi-Jeong Park; Hyun-Kyu Yu; Cheon-Soo Kim (MWSCAS, 2014)

Untrimmed BGR of 1.1% $3 sigma$ Based on Dynamic-Biased Op Amp With Reduced ${V} _{ rm off}$. - Jayol Lee; Cheon-Soo Kim; Jang Hong Choi; Ki Su Kim; Bon Tae Koo (IEEE Trans. Circuits Syst. II Express Briefs, 2020)