Hardware emulation board based on FPGAs and programmable interconnections. - W. Y. Lo; Chiu-sing Choy; Cheong-Fat Chan (RSP, 1994)

A Feedback Control Circuit Design Technique to Suppress Power Noise in High Speed Output Driver. - Chiu-sing Choy; Cheong-Fat Chan; M. H. Ku (ISCAS, 1995)

Test Generation with Dynamic Probe Points in High Observability Testing Environment. - Oliver Chiu-sing Choy; Lap-kong Chan; Ray Chan; Cheong-Fat Chan (IEEE Trans. Computers, 1996)

Self-timed 1-D ICT processor. - Tin-Chak Johnson Pang; Oliver Chiu-sing Choy; Cheong-Fat Chan; Wai-kuen Cham (ASP-DAC, 1997)

A Useful Micropipeline Architecture to Implement DSP Algorithms. - Oliver Chiu-sing Choy; Tin-Chak Johnson Pang; Juraj Povazanec; Cheong-Fat Chan (EUROMICRO, 1998)

Asynchronous logic in bit-serial arithmetic. - Juraj Povazanec; Chiu-Sing Choy; Cheong-Fat Chan (ICECS, 1998)

Pipelined Dataflow Architecture of a Small Processor. - Juraj Povazanec; Oliver Chiu-sing Choy; Cheong-Fat Chan; Jan Butas; Yeu-qiu Zhang; Jing-Ling Yang; Tin-yan Tang (PDPTA, 1999)

A four-phase handshaking asynchronous static RAM design for self-timed systems. - Vincent Wing-Yun Sit; Chiu-Sing Choy; Cheong-Fat Chan (IEEE J. Solid State Circuits, 1999)

A self-timed ICT chip for image coding. - Tin-Chak Johnson Pang; Oliver Chiu-sing Choy; Cheong-Fat Chan; Wai-kuen Cham (IEEE Trans. Circuits Syst. Video Technol., 1999)

Design of self-timed asynchronous Booth's multiplier. - Tin-Y. Tang; Chiu-sing Choy; Pui-Lam Siu; Cheong-Fat Chan (ASP-DAC, 2000)

An 8×8 adiabatic quasi-static CMOS multiplier. - Wing-Sum Mak; Cheong-Fat Chan; Ka-Wai Cheung; Chiu-Sing Choy (ISCAS, 2000)

An ALU design using a novel asynchronous pipeline architecture. - Tin-Yau Tang; Chiu-sing Choy; Jan Butas; Cheong-Fat Chan (ISCAS, 2000)

CMOS high speed interpolators based on parallel architecture. - Hongwei Wang; Cheong-Fat Chan; Chiu-sing Choy (IEEE Trans. Consumer Electron., 2000)

High speed CMOS digital-to-analog converter with linear interpolator. - Hongwei Wang; Cheong-Fat Chan; Chiu-sing Choy (IEEE Trans. Consumer Electron., 2000)

A pipelined dataflow small micro-coded asynchronous processor and its application to DCT. - Chi-Wai Lee; Chiu-sing Choy; Jan Butas; Cheong-Fat Chan (ISCAS (4), 2001)

A giga-hertz CMOS digital controlled oscillator. - Lai-Kan Leung; Cheong-Fat Chan; Oliver Chiu-sing Choy (ISCAS (4), 2001)

A low power asynchronous DES. - Pui-Lam Siu; Chiu-sing Choy; Jan Butas; Cheong-Fat Chan (ISCAS (4), 2001)

Asynchronous cross-pipelined multiplier. - Jan Butas; Chiu-Sing Choy; Juraj Povazanec; Cheong-Fat Chan (IEEE J. Solid State Circuits, 2001)

A self-timed divider using a new fast and robust pipeline scheme. - Jing-Ling Yang; Chiu-Sing Choy; Cheong-Fat Chan (IEEE J. Solid State Circuits, 2001)

A New Control Circuit for Asynchronous Micropipelines. - Oliver Chiu-sing Choy; Jan Butas; Juraj Povazanec; Cheong-Fat Chan (IEEE Trans. Computers, 2001)

A 900 MHz 1.2 V CMOS mixer with high linearity. - Wang-Chi Cheng; Cheong-Fat Chan; Oliver Chiu-sing Choy; Kong-Pang Pun (APCCAS (1), 2002)

A Totally Self-Checking Dynamic Asynchronous Datapath. - Jing-Ling Yang; Oliver Chiu-sing Choy; Cheong-Fat Chan; Kong-Pang Pun (Asian Test Symposium, 2002)

A 1.2 V 900 MHz CMOS mixer. - Wang-Chi Cheng; Cheong-Fat Chan; Oliver Chiu-sing Choy; Kong-Pang Pun (ISCAS (5), 2002)

A CMOS current feedback operational amplifier with active current mode compensation. - Kin-Pui Ho; Cheong-Fat Chan; Chiu-sing Choy; Kong-Pang Pun (ISCAS (1), 2002)

A quadrature IF mixer with high image rejection for continuous-time complex Sigma-Delta modulators. - Kong-Pang Pun; Chiu-sing Choy; Cheong-Fat Chan; José E. Franca (ISCAS (4), 2002)

A 12-bit 80 Ms/s 110 mW floating analog-to-digital converter. - Hongwei Wang; Cheong-Fat Chan; Chiu-sing Choy (ISCAS (3), 2002)

An HMM-based speech recognition IC. - Wei Han; Kwok-Wai Hon; Cheong-Fat Chan; Tan Lee 001; Chiu-sing Choy; Kong-Pang Pun; Pak-Chung Ching (ISCAS (2), 2003)

A low power asynchronous GF(2173) ALU for elliptic curve crypto-processor. - Pak-Keung Leung; Chiu-sing Choy; Cheong-Fat Chan; Kong-Pang Pun (ISCAS (5), 2003)

Clock recovery circuit with adiabatic technology (quasi-static CMOS logic). - W. K. Yeung; Cheong-Fat Chan; Chiu-sing Choy; Kong-Pang Pun (ISCAS (2), 2003)

Design for Self-Checking and Self-Timed Datapath. - Jing-Ling Yang; Oliver Chiu-sing Choy; Cheong-Fat Chan; Kong-Pang Pun (VTS, 2003)

Reversed nested Miller compensation with voltage buffer and nulling resistor. - Kin-Pui Ho; Cheong-Fat Chan; Chiu-Sing Choy; Kong-Pang Pun (IEEE J. Solid State Circuits, 2003)

A low power asynchronous Java processor for contactless smart card. - Chun-Pong Yu; Chiu-sing Choy; Hao Min; Cheong-Fat Chan; Kong-Pang Pun (ASP-DAC, 2004)

Card-Centric Framework - Providing I/O Resources for Smart Cards. - Pak-Kee Chan; Oliver Chiu-sing Choy; Cheong-Fat Chan; Kong-Pang Pun (CARDIS, 2004)

An IF input continuous-time sigma-delta analog-digital converter with high image rejection. - Junhua Shen; Kong-Pang Pun; Chiu-sing Choy; Cheong-Fat Chan (ICECS, 2004)

An asynchronous SOVA decoder for wireless communication application. - Wing-Kin Chan; Chiu-sing Choy; Cheong-Fat Chan; Kong-Pang Pun (ISCAS (2), 2004)

An IF-sampling SC complex lowpass Sigma Delta modulator with high image rejection by capacitor sharing. - Wang Tung Cheng; Kong-Pang Pun; Cheong-Fat Chan; Chiu-sing Choy (ISCAS (1), 2004)

Pipelines in Dynamic Dual-Rail Circuits. - Jing-Ling Yang; Oliver Chiu-sing Choy; Cheong-Fat Chan; Kong-Pang Pun (PATMOS, 2004)

A high-efficiency strongly self-checking asynchronous datapath. - Jing-Ling Yang; Chiu-sing Choy; Cheong-Fat Chan; Kong-Pang Pun (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

A low-latency asynchronous shift register. - Ragnarok Pak-Kee Chan; Oliver Chiu-sing Choy; Cheong-Fat Chan; Kong-Pang Pun (IEEE Trans. Circuits Syst. II Express Briefs, 2004)

An I/Q mismatch-free switched-capacitor complex sigma-delta Modulator. - Kong-Pang Pun; Chiu-sing Choy; Cheong-Fat Chan; José Epifânio da Franca (IEEE Trans. Circuits Syst. II Express Briefs, 2004)

Preparing smartcard for the future: from passive to active. - Pak-Kee Chan; Chiu-sing Choy; Cheong-Fat Chan; Kong-Pang Pun (IEEE Trans. Consumer Electron., 2004)

High Speed Curve Interpolating D/A Converter. - Hongwei Wang; Cheong-Fat Chan; Chiu-sing Choy (J. VLSI Signal Process., 2004)

A 75dB image rejection IF-input quadrature sampling SC ΣΔ modulator. - Wang Tung Cheng; Kong-Pang Pun; Chiu-Sing Choy; Cheong-Fat Chan (ESSCIRC, 2005)

A speech recognizer with selectable model parameters. - Wei Han; Cheong-Fat Chan; Chiu-sing Choy; Kong-Pang Pun (ISCAS (6), 2005)

Realization of card-centric framework: a card-centric computer [smart cards]. - Chi-Leung San; Chiu-sing Choy; Pak-Kee Chan; Cheong-Fat Chan; Kong-Pang Pun (ISCAS (5), 2005)

Ramp voltage supply using adiabatic charging principle. - Pui-Tak So; Cheong-Fat Chan; Chiu-sing Choy; Kong-Pang Pun (ISCAS (3), 2005)

Active RC filter with reduced capacitance by current division technique. - Nang-Ching Yeung; Kong-Pang Pun; Oliver Chiu-sing Choy; Cheong-Fat Chan (ISCAS (4), 2005)

Sub-1 V Current Mode CMOS Integrated Receiver Front-end for GPS System. - Wang-Chi Cheng; Cheong-Fat Chan; Kong-Pang Pun; Oliver Chiu-sing Choy (APCCAS, 2006)

0.8 V GPS band CMOS VCO with 29% Tuning Range. - Wang-Chi Cheng; Cheong-Fat Chan; Kong-Pang Pun; Oliver Chiu-sing Choy (APCCAS, 2006)

0.7 V Monolithic CMOS LNA for 802.11 A/B WLAN Application. - Wang-Chi Cheng; Cheong-Fat Chan; Suyi Tao; King-Keung Mok (APCCAS, 2006)

Adiabatic Smart Card. - King-Keung Mok; Ka-Hung Tsang; Cheong-Fat Chan; Oliver Chiu-sing Choy; Kong-Pang Pun (APCCAS, 2006)

A 6-digit CMOS current-mode analog-to-quaternary converter with RSD error correction algorithm. - Chi-Hong Chan; Cheong-Fat Chan; Oliver Chiu-sing Choy; Kong-Pang Pun (ISCAS, 2006)

An efficient MFCC extraction method in speech recognition. - Wei Han; Cheong-Fat Chan; Oliver Chiu-sing Choy; Kong-Pang Pun (ISCAS, 2006)

A 0.5V fully differential OTA with local common feedback. - Xiao-Yong He; Kong-Pang Pun; Oliver Chiu-sing Choy; Cheong-Fat Chan (ISCAS, 2006)

An optimal normal basis elliptic curve cryptoprocessor for inductive RFID application. - Pak-Keung Leung; Oliver Chiu-sing Choy; Cheong-Fat Chan; Kong-Pang Pun (ISCAS, 2006)

A fully differential low noise amplifier with real-time channel hopping for ultra-wideband wireless applications. - Siu-Kei Tang; Kong-Pang Pun; Oliver Chiu-sing Choy; Cheong-Fat Chan (ISCAS, 2006)

Power-efficient VLSI implementation of bitstream parsing in H.264/AVC decoder. - Ke Xu 014; Oliver Chiu-sing Choy; Cheong-Fat Chan; Kong-Pang Pun (ISCAS, 2006)

A 75-dB image rejection IF-input quadrature-sampling SC ΣΔ Modulator. - Kong-Pang Pun; Wang Tung Cheng; Chiu-Sing Choy; Cheong-Fat Chan (IEEE J. Solid State Circuits, 2006)

Priority-Based Heading One Detector in H.264/AVC Decoding. - Ke Xu 014; Oliver Chiu-sing Choy; Cheong-Fat Chan; Kong-Pang Pun (EURASIP J. Embed. Syst., 2007)

Power-Efficient VLSI Realization of a Complex FSM for H.264/AVC Bitstream Parsing. - Ke Xu 014; Chiu-sing Choy; Cheong-Fat Chan; Kong-Pang Pun (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

A Speech Recognition IC Using Hidden Markov Models with Continuous Observation Densities. - Wei Han; Kwok-Wai Hon; Cheong-Fat Chan; Oliver Chiu-sing Choy; Kong-Pang Pun (J. VLSI Signal Process., 2007)

Enhanced channel selection using digital low-IF in Weaver receiver architecture. - Misteltein Pak-Kee Chan; Oliver Chiu-sing Choy; Kong-Pang Pun; Cheong-Fat Chan; Alex Ka Nang Leung (APCCAS, 2008)

A Fully Differential Band-Selective Low-Noise Amplifier for MB-OFDM UWB Receivers. - Siu-Kei Tang; Kong-Pang Pun; Oliver Chiu-sing Choy; Cheong-Fat Chan; Ka Nang Leung (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

A Novel Mismatch Cancellation and I/Q Channel Multiplexing Scheme for Quadrature Bandpass DeltaSigma Modulators. - Bing Li; Cheong-Fat Chan; Kong-Pang Pun; Oliver Chiu-sing Choy (ISCAS, 2009)