Least mean square adaptive digital background calibration of pipelined analog-to-digital converters. - Yun Chiu; Cheongyuen W. Tsang; Borivoje Nikolic; Paul R. Gray (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

Background ADC calibration in digital domain. - Cheongyuen W. Tsang; Yun Chiu; Johan P. Vanderhaegen; Sebastian Hoyos; Charles Chen; Robert W. Brodersen; Borivoje Nikolic (CICC, 2008)

A 15 MHz - 600 MHz, 20 mW, 0.38 mm2, fast coarse locking digital DLL in 0.13μm CMOS. - Sebastian Hoyos; Cheongyuen W. Tsang; Johan P. Vanderhaegen; Yun Chiu; Yasutoshi Aibara; Haideh Khorramabadi; Borivoje Nikolic (ESSCIRC, 2008)

A 15 MHz to 600 MHz, 20 mW, 0.38 mm2 Split-Control, Fast Coarse Locking Digital DLL in 0.13 µ m CMOS. - Sebastian Hoyos; Cheongyuen W. Tsang; Johan P. Vanderhaegen; Yun Chiu; Yasutoshi Aibara; Haideh Khorramabadi; Borivoje Nikolic (IEEE Trans. Very Large Scale Integr. Syst., 2012)

16.5 An 8GS/s time-interleaved SAR ADC with unresolved decision detection achieving -58dBFS noise and 4GHz bandwidth in 28nm CMOS. - John P. Keane; Nathaniel J. Guilar; Dusan Stepanovic; Bernd Wuppermann; Charles Wu; Cheongyuen W. Tsang; Robert Neff; Ken Nishimura (ISSCC, 2017)