Rapid-prototyping of high-assurance systems. - Richard Auletta; Cherrice Traver (Great Lakes Symposium on VLSI, 1993)

A Comparison of Synchronous and Asynchronous FSMD Designs. - Richard Auletta; Robert B. Reese; Cherrice Traver (ICCD, 1993)

Analyzing and verifying locally clocked circuits with the concurrency workbench. - Garth Baulch; David Hemmendinger; Cherrice Traver (Great Lakes Symposium on VLSI, 1995)

Guest Editorial Introduction to the Special Issue on the 1995 IEEE ASIC Conference. - K. W. Hsu; Cherrice Traver (IEEE Trans. Very Large Scale Integr. Syst., 1996)

The multidisciplinary international virtual design studio (MIVDS). - Abdülkadir Erden; Aydan M. Erkmen; Ismet Erkmen; Ronald B. Bucinell; Cherrice Traver; Leila Notash (IEEE Trans. Educ., 2000)

Arithmetic Logic Circuits Using Self-Timed Bit Level Dataflow and Early Evaluation. - Robert B. Reese; Mitchell A. Thornton; Cherrice Traver (ICCD, 2001)

Generalized Early Evaluation in Self-Timed Circuits. - Mitchell A. Thornton; Kenneth Fazel; Robert B. Reese; Cherrice Traver (DATE, 2002)

A Fine-Grain Phased Logic CPU. - Robert B. Reese; Mitchell A. Thornton; Cherrice Traver (ISVLSI, 2003)

Performance enhancement in phased logic circuits using automatic slack-matching buffer insertion. - Kenneth Fazel; Lun Li; Mitchell A. Thornton; Robert B. Reese; Cherrice Traver (ACM Great Lakes Symposium on VLSI, 2004)

A Coarse-Grain Phased Logic CPU. - Robert B. Reese; Mitchell A. Thornton; Cherrice Traver (IEEE Trans. Computers, 2005)

Early evaluation for performance enhancement in phased logic. - Robert B. Reese; Mitchell A. Thornton; Cherrice Traver; David Hemmendinger (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)