An optimization algorithm for simultaneous routing and buffer insertion with delay-power constraints in VLSI layout design. - Chessda Uttraphan; Nasir Shaikh-Husin; Mohamed Khalil Hani (ISQED, 2014)

An optimized buffer insertion algorithm with delay-power constraints for VLSI layouts. - Chessda Uttraphan; Nasir Shaikh-Husin; Mohamed Khalil Hani (Turkish J. Electr. Eng. Comput. Sci., 2017)

Optimizing FPGA-based YOLO series accelerators: A survey of techniques. - Chua Wee Heng; Chessda Uttraphan; Chew Chang Choon; Kok Boon Ching (Neurocomputing, 2025)